Datasheet > CDK1307DILP40

CDK1307DILP40

更新时间： 2024-01-17 08:38:27

品牌	Logo	应用领域
CADEKA		转换器
页数	文件大小	规格书
15页	1149K
描述
Ultra Low Power, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters (ADCs)

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CDK1307DILP40 数据手册

ADVANCE Data Sheet

Amplify the Human Experience

CDK1307

Ultra Low Power, 20/40/65/80MSPS,

12/13-bit Analog-to-Digital Converters (ADCs)

F E A T U R E S

General Description

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13-bit resolution

The CDK1307 is a high performance ultra low power Analog-to-Digital

Converter (ADC). The ADC employs internal reference circuitry, a CMOS

control interface and CMOS output data, and is based on a proprietary struc-

ture. Digital error correction is employed to ensure no missing codes in the

complete full scale range.

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20/40/65/80MSPS max sampling rate

Ultra-Low Power Dissipation:

19/33/50/60mW

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72.4dB SNR at 8MHz F_IN

Internal reference circuitry

1.8V core supply voltage

1.7 – 3.6V I/O supply voltage

Parallel CMOS output

Two idle modes with fast startup times exist. The entire chip can either be

put in Standby Mode or Power Down mode. The two modes are optimized to

allow the user to select the mode resulting in the smallest possible energy

consumption during idle mode and startup.

40-pin QFN package

Pin compatible with CDK1308

The CDK1307 has a highly linear THA optimized for frequencies up to Nyquist.

The differential clock interface is optimized for low jitter clock sources and

supports LVDS, LVPECL, sine wave, and CMOS clock inputs.

A P P L I C A T I O N S

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Medical Imaging

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Portable Test Equipment

Functional Block Diagram

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Digital Oscilloscopes

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IF Communication

Ordering Information

Part Number

Speed

Package

QFN-40

Pb-Free RoHS Compliant Operating Temperature Range Packaging Method

CDK1307AILP40

CDK1307BILP40

CDK1307CILP40

CDK1307DILP40

20MSPS

40MSPS

65MSPS

80MSPS

Yes

-40°C to +85°C

Tray

Moisture sensitivity level for all parts is MSL-3.

www.cadeka.com

12 3 4 5 6 7...15

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