Datasheet > CDK-2000-CLK

CDK-2000-CLK

更新时间： 2024-01-30 22:56:03

品牌	Logo	应用领域
凌云 - CIRRUS		时钟
页数	文件大小	规格书
28页	516K
描述
Fractional-N Clock Multiplier

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中文翻译

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数据手册

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CDK-2000-CLK 数据手册

CS2100-OTP

Fractional-N Clock Multiplier

Features

General Description

The CS2100-OTP is an extremely versatile system

clocking device that utilizes a programmable phase lock

loop. The CS2100-OTP is based on a hybrid analog-

digital PLL architecture comprised of a unique combina-

Clock Multiplier / Jitter Reduction

–

Generates a Low Jitter 6 - 75 MHz Clock

from a Jittery or Intermittent 50 Hz to

30 MHz Clock Source

tion of

Delta-Sigma Fractional-N Frequency

Highly Accurate PLL Multiplication Factor

Synthesizer and a Digital PLL. This architecture allows

for generation of a low-jitter clock relative to an external

noisy synchronization clock with frequencies as low as

50 Hz. The CS2100-OTP has many configuration op-

tions which are set once prior to runtime. At runtime

there are three hardware configuration pins available for

mode and feature selection.

–

Maximum Error Less Than 1 PPM in High-

Resolution Mode

One-Time Programmability

–

Configurable Hardware Control Pins

Configurable Auxiliary Output

Flexible Sourcing of Reference Clock

The CS2100-OTP is available in a 10-pin MSOP pack-

age in Commercial (-10°C to +70°C) grade. Customer

development kits are also available for custom device

prototyping, small production programming, and device

evaluation. Please see “Ordering Information” on

page 28 for complete details.

–

External Oscillator or Clock Source

Supports Inexpensive Local Crystal

Minimal Board Space Required

–

No External Analog Loop-filter

Components

3.3 V

Timing Reference

Frequency Reference

PLL Output

Hardware

Hardware Configuration

Control

Auxiliary

Output

Lock Indicator

8 MHz to 75 MHz

Low-Jitter Timing

Reference

Fractional-N

Frequency Synthesizer

6 to 75 MHz

PLL Output

50 Hz to 30 MHz

Frequency

Digital PLL &

Reference

Fractional N Logic

Output to Input

Clock Ratio

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Preliminary Product Information

JUN '08

DS841PP1

http://www.cirrus.com

12 3 4 5 6 7...28

中文翻译

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与CDK-2000-CLK相关器件

型号	品牌	获取价格	描述	数据表
CDK2000-CLK	CIRRUS	获取价格	Fractional-N Clock Multiplier
CDK-2000-LCO	CIRRUS	获取价格	Fractional-N Clock Multiplier with Internal LCO
CDK2000-LCO	CIRRUS	获取价格	Fractional-N Clock Multiplier with Internal LCO
CDK2307	CADEKA	获取价格	Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
CDK2307_2B	CADEKA	获取价格	Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
CDK2307AILP64	CADEKA	获取价格	Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
CDK2307AILP64X	CADEKA	获取价格	Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
CDK2307AITQ64	CADEKA	获取价格	Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
CDK2307BILP64	CADEKA	获取价格	Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters
CDK2307BILP64X	CADEKA	获取价格	Dual, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters

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