CD74HCT75EE4

更新时间： 2024-02-05 10:30:38

品牌	Logo	应用领域
德州仪器 - TI		锁存器
页数	文件大小	规格书
15页	360K
描述
Dual 2-Bit Bistable Transparent Latch

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数据手册

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CD74HCT75EE4 数据手册

CD54HC75, CD74HC75, CD54HCT75, CD74HCT75

Test Circuits and Waveforms (Continued)

t C

90%

10%

2.7V

0.3V

CLOCK

INPUT

CLOCK

INPUT

50%

1.3V

GND

H(L)

H(H)

H(L)

DATA

INPUT

DATA

INPUT

50%

1.3V

SU(L)

1.3V

GND

SU(H)

SU(L)

90%

50%

THL

TLH

THL

TLH

90%

1.3V

90%

1.3V

OUTPUT

10%

PLH

PHL

PLH

REM

SET, RESET

OR PRESET

SET, RESET

OR PRESET

50%

1.3V

GND

50pF

FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 8. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE

TRIGGERED SEQUENTIAL LOGIC CIRCUITS

1...4 5 678 9 10...15

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