CD74HCT75EE4

更新时间： 2024-01-18 11:03:45

品牌	Logo	应用领域
德州仪器 - TI		锁存器
页数	文件大小	规格书
15页	360K
描述
Dual 2-Bit Bistable Transparent Latch

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数据手册

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CD74HCT75EE4 数据手册

CD54HC75, CD74HC75, CD54HCT75, CD74HCT75

Switching Speciﬁcations Input t , t = 6ns (Continued)

25 C

-40 C TO 85 C -55 C TO 125 C

TEST

PARAMETER

Propagation Delay,

SYMBOL CONDITIONS (V)

MIN TYP MAX

MIN

MAX

MIN

MAX

UNITS

, t

C = 50pF

4.5

PLH PHL

Enable to Q

C = 15pF

Output Transition Time

Input Capacitance

, t

TLH THL

C = 50pF

4.5

Power Dissipation Capacitance

(Notes 3, 4)

NOTES:

3. C

is used to determine the dynamic power consumption, per latch.

4. P = V

f (C

+ C ) where f = input frequency, C = output load capacitance, V

= supply voltage.

Test Circuits and Waveforms

+ t

t C = 6ns

+ t

t C = 6ns

t C

90%

10%

2.7V

CLOCK

50%

10%

1.3V

0.3V

50%

1.3V

0.3V

GND

NOTE: Outputs should be switching from 10% V

to 90% V

NOTE: Outputs should be switching from 10% V

to 90% V

accordance with device truth table. For f

, input duty cycle = 50%.

accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

t = 6ns

90%

50%

10%

2.7V

1.3V

0.3V

INPUT

GND

THL

TLH

THL

TLH

90%

1.3V

90%

50%

10%

INVERTING

OUTPUT

INVERTING

OUTPUT

10%

PLH

PHL

PLH

PHL

FIGURE 5. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

1...3 4 567 8 9...15

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