是否无铅: | 不含铅 | 是否Rohs认证: | 符合 |
生命周期: | Obsolete | 零件包装代码: | DIP |
包装说明: | DIP-14 | 针数: | 14 |
Reach Compliance Code: | compliant | HTS代码: | 8542.39.00.01 |
风险等级: | 5.59 | Is Samacsys: | N |
系列: | HCT | JESD-30 代码: | R-PDIP-T14 |
JESD-609代码: | e4 | 长度: | 19.305 mm |
负载电容(CL): | 50 pF | 逻辑集成电路类型: | J-K FLIP-FLOP |
最大频率@ Nom-Sup: | 19000000 Hz | 最大I(ol): | 0.004 A |
位数: | 2 | 功能数量: | 2 |
端子数量: | 14 | 最高工作温度: | 125 °C |
最低工作温度: | -55 °C | 输出极性: | COMPLEMENTARY |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | DIP |
封装等效代码: | DIP14,.3 | 封装形状: | RECTANGULAR |
封装形式: | IN-LINE | 峰值回流温度(摄氏度): | NOT SPECIFIED |
电源: | 5 V | 传播延迟(tpd): | 65 ns |
认证状态: | Not Qualified | 座面最大高度: | 5.08 mm |
子类别: | FF/Latches | 最大供电电压 (Vsup): | 5.5 V |
最小供电电压 (Vsup): | 4.5 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | NO | 技术: | CMOS |
温度等级: | MILITARY | 端子面层: | Nickel/Palladium/Gold (Ni/Pd/Au) |
端子形式: | THROUGH-HOLE | 端子节距: | 2.54 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | NOT SPECIFIED |
触发器类型: | NEGATIVE EDGE | 宽度: | 7.62 mm |
最小 fmax: | 19 MHz | Base Number Matches: | 1 |
型号 | 品牌 | 替代类型 | 描述 | 数据表 |
CD74HCT107E | TI |
类似代替 |
Dual J-K Flip-Flop with Reset Negative-Edge Trigger |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
CD74HCT107EN | ETC |
获取价格 |
Logic IC | |
CD74HCT107EX | RENESAS |
获取价格 |
IC,FLIP-FLOP,DUAL,J/K TYPE,HCT-CMOS,DIP,14PIN,PLASTIC | |
CD74HCT107F | ETC |
获取价格 |
Logic IC | |
CD74HCT107H | ETC |
获取价格 |
J-K-Type Flip-Flop | |
CD74HCT107M | RENESAS |
获取价格 |
IC,FLIP-FLOP,DUAL,J/K TYPE,HCT-CMOS,SOP,14PIN,PLASTIC | |
CD74HCT107M | ROCHESTER |
获取价格 |
HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 | |
CD74HCT107M96 | RENESAS |
获取价格 |
J-K Flip-Flop, HCT Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, C | |
CD74HCT109 | TI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger | |
CD74HCT109E | TI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger | |
CD74HCT109EE4 | TI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger |