CD74HCT109

更新时间： 2024-09-28 23:04:27

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
8页	60K
描述
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

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数据手册

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CD74HCT109 数据手册

CD74HC109,

CD74HCT109

Data sheet acquired from Harris Semiconductor

SCHS140

Dual J-K Flip-Flop with Set and Reset

Positive-Edge Trigger

March 1998

at V

= 5V

Features

• HCT Types

• Asynchronous Set and Reset

• Schmitt Trigger Clock Inputs

• Typical Propagation Delay = 18ns at V

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

[ /Title

(CD74H

C109,

= 5V,

V = 0.8V (Max), V = 2V (Min)

IL IH

C = 15pF, T = 25 C

- CMOS Input Compatibility, I ≤ 1µA at V , V

OL OH

CD74H

CT109)

/Subject

(Dual J-

K Flip-

Flop

with Set

and

Reset

• Typical f

= 60MHz at V

= 5V, C = 15pF,

MAX

T = 25 C

Description

• Fanout (Over Temperature Range)

The Harris CD74HC109 and CD74HCT109 are dual J-K ﬂip-

ﬂops with set and reset. The ﬂip-ﬂop changes state with the

positive transition of Clock (1CP and 2CP).

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

The ﬂip-ﬂop is set and reset by active-low S and R,

respectively. A low on both the set and reset inputs

simultaneously will force both Q and Q outputs high.

However, both set and reset going high simultaneously

results in an unpredictable output condition.

• Wide Operating Temperature Range . . . -55 C to 125 C

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

Ordering Information

• HC Types

- 2V to 6V Operation

TEMP. RANGE

PKG.

NO.

- High Noise Immunity: N = 30%, N = 30% of V

IL IH CC

PART NUMBER

( C)

PACKAGE

Pinout

CD74HC109, CD74HCT109

(PDIP, SOIC)

TOP VIEW

16 V

15 2R

14 2J

13 2K

12 2CP

11 2S

10 2Q

1CP

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1667.1

12 3 4 5 6 7 8

中文翻译

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