是否Rohs认证: | 不符合 | 生命周期: | Obsolete |
包装说明: | DIP, DIP14,.3 | Reach Compliance Code: | not_compliant |
风险等级: | 5.69 | JESD-30 代码: | R-PDIP-T14 |
JESD-609代码: | e0 | 负载电容(CL): | 50 pF |
逻辑集成电路类型: | J-K FLIP-FLOP | 最大频率@ Nom-Sup: | 20000000 Hz |
最大I(ol): | 0.004 A | 功能数量: | 2 |
端子数量: | 14 | 最高工作温度: | 125 °C |
最低工作温度: | -55 °C | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | DIP | 封装等效代码: | DIP14,.3 |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
电源: | 2/6 V | 子类别: | FF/Latches |
表面贴装: | NO | 技术: | CMOS |
温度等级: | MILITARY | 端子面层: | Tin/Lead (Sn/Pb) |
端子形式: | THROUGH-HOLE | 端子节距: | 2.54 mm |
端子位置: | DUAL | 触发器类型: | NEGATIVE EDGE |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
CD74HC107F | ETC |
获取价格 |
Logic IC |
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CD74HC107H | ETC |
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J-K-Type Flip-Flop |
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CD74HC107M | TI |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger |
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CD74HC107M96 | TI |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger |
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CD74HC107M96E4 | TI |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger |
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CD74HC107M96G4 | TI |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger |
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CD74HC107ME4 | TI |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger |
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CD74HC107MG4 | TI |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger |
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CD74HC107MT | TI |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger |
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CD74HC107MTE4 | TI |
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Dual J-K Flip-Flop with Reset Negative-Edge Trigger |
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