CD4020BMS, CD4024BMS,
CD4040BMS
CMOS Ripple-Carry Binary
Counter/Dividers
October 1996
Features
Pinouts
CD4020BMS
TOP VIEW
• High Voltage Types (20V Rating)
• Medium Speed Operation
• Fully Static Operation
Q12
Q13
Q14
Q6
1
2
3
4
5
6
7
8
16 VDD
15 Q11
14 Q10
13 Q8
• Buffered Inputs and Outputs
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• Common Reset
Q5
12 Q9
• 5V, 10V and 15V Parametric Ratings
Q7
11 RESET
• Maximum Input Current of 1µa at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25oC
10
9
θ
Q4
Q1
VSS
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
CD4024BMS
TOP VIEW
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications For Description Of
‘B’ Series CMOS Devices”
θ
1
14 VDD
13 NC
12 Q1
11 Q2
10 NC
RESET
Q7
2
3
4
5
6
7
Applications
• Control Counters
• Timers
Q6
Q5
• Frequency Dividers
• Time-Delay Circuits
Q4
9
8
Q3
NC
VSS
Description
NC = NO CONNECTION
CD4020BMS - 14 Stage
CD4024BMS - 7 Stage
CD4040BMS - 12 Stage
CD4040BMS
TOP VIEW
CD4020BMS, CD4024BMS, and CD4040BMS are ripple-
carry binary counters. All counter stages are master-slave
flip-flops. The state of a counter advances one count on the
negative transition of each input pulse; a high level on the
RESET line resets the counter to its all zeros state. Schmitt
trigger action on the input-pulse line permits unlimited rise
and fall times. All inputs and outputs are buffered.
Q12
Q6
1
2
3
4
5
6
7
8
16 VDD
15 Q11
14 Q10
13 Q8
12 Q9
11 R
Q5
Q7
Q4
Q3
The CD4020BMS, CD4024BMS and the CD4040BMS is
supplied in these 14 lead outline packages:
10
9
θ
Q2
Q1
VSS
CD4020B
H4W
CD4024B
H4Q
CD4040B
H4X
Braze Seal DIP
Frit Seal DIP
H1F
H1B
H1F
H6W
H3W
H6W
Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3300.1
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7-359