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CAT9552HV6I-G

更新时间： 2024-02-14 13:31:19
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器
页数 文件大小 规格书
18页 330K
描述
16-Channel I2C-bus LED Driver with Programmable Blink Rate

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CAT9552HV6I-G 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFN包装说明：HVQCCN, LCC24,.16SQ,20
针数：24Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.27数据输入模式：SERIAL
接口集成电路类型：LED DISPLAY DRIVERJESD-30 代码：S-XQCC-N24
JESD-609代码：e4长度：4 mm
复用显示功能：NO功能数量：1
区段数：16端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC24,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2.5/5 V认证状态：Not Qualified
座面最大高度：0.8 mm子类别：Display Drivers
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：3 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4 mm
最小 fmax：0.4 MHzBase Number Matches：1

CAT9552HV6I-G 数据手册

 浏览型号CAT9552HV6I-G的Datasheet PDF文件第5页浏览型号CAT9552HV6I-G的Datasheet PDF文件第6页浏览型号CAT9552HV6I-G的Datasheet PDF文件第7页浏览型号CAT9552HV6I-G的Datasheet PDF文件第9页浏览型号CAT9552HV6I-G的Datasheet PDF文件第10页浏览型号CAT9552HV6I-G的Datasheet PDF文件第11页 
CAT9552  
The Control Register acts as a pointer to determine  
which register will be written or read. The four least  
significant bits, B0, B1, B2, B3, are used to select  
which internal register is accessed, according  
to the Table 1.  
Acknowledge  
After a successful data transfer, each receiving device  
is required to generate an acknowledge. The  
acknowledging device pulls down the SDA line during  
the ninth clock cycle, signaling that it received the 8  
bits of data. The SDA line remains stable LOW during  
the HIGH period of the acknowledge related clock  
pulse (Figure 4).  
If the auto increment flag is set (AI = 1), the four least  
significant bits of the Control Register are  
automatically incremented after a read or write  
operation. This allows the user to access the  
CAT9552 internal registers sequentially. The content  
of these bits will rollover to “0000” after the last  
register is accessed.  
The CAT9552 responds with an acknowledge after  
receiving a START condition and its slave address. If  
the device has been selected along with a write  
operation, it responds with an acknowledge after  
receiving each 8- bit byte.  
Table 1. Internal Registers Selection  
Register  
Name  
Register  
Function  
When the CAT9552 begins a READ mode it transmits  
8 bits of data, releases the SDA line, and monitors the  
line for an acknowledge. Once it receives this  
acknowledge, the CAT9552 will continue to transmit  
data. If no acknowledge is sent by the Master, the  
device terminates data transmission and waits for a  
STOP condition. The master must then issue a stop  
condition to return the CAT9552 to the standby power  
mode and place the device in a known state.  
B3  
B2  
B1  
B0  
Type  
Input  
Register 0  
0
0
0
0
INPUT0  
INPUT1  
PSC0  
PWM0  
PSC1  
PWM1  
LS0  
READ  
Input  
Register 1  
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
READ  
READ/  
WRITE  
Frequency  
Prescaler 0  
READ/  
WRITE  
PWM  
Register 0  
READ/  
WRITE  
Frequency  
Prescaler 1  
Registers and Bus Transactions  
READ/  
WRITE  
PWM  
Register 1  
After the successful acknowledgement of the slave  
address, the bus master will send a command byte to  
the CAT9552 which will be stored in the Control  
Register. The format of the Control Register is shown  
in Figure 5.  
READ/  
WRITE  
LED 0-3  
Selector  
READ/  
WRITE  
LED 4-7  
Selector  
LS1  
READ/  
WRITE  
LED 8-11  
Selector  
LS2  
READ/  
WRITE  
LED 12-15  
Selector  
LS3  
SCL FROM  
MASTER  
1
8
9
DATA OUTPUT  
FROM TRANSMITTER  
DATA OUTPUT  
FROM RECEIVER  
START  
ACKNOWLEDGE  
Figure 4. Acknowledge Timing  
0
0
0
AI  
B3  
B2  
B1  
B0  
REGISTER ADDRESS  
AUTO-INCREMENT FLAG  
RESET STATE: 00h  
Figure 5. Control Register  
Doc. No. MD-9005 Rev D  
8
© 2010 SCILLC. All rights reserved  
Characteristics subject to change without notice  
1...567891011...18

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