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CAT9552HV6I-G

更新时间: 2024-02-16 09:05:29
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器
页数 文件大小 规格书
18页 330K
描述
16-Channel I2C-bus LED Driver with Programmable Blink Rate

CAT9552HV6I-G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:HVQCCN, LCC24,.16SQ,20
针数:24Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.27数据输入模式:SERIAL
接口集成电路类型:LED DISPLAY DRIVERJESD-30 代码:S-XQCC-N24
JESD-609代码:e4长度:4 mm
复用显示功能:NO功能数量:1
区段数:16端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC24,.16SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2.5/5 V认证状态:Not Qualified
座面最大高度:0.8 mm子类别:Display Drivers
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:3 V表面贴装:YES
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4 mm
最小 fmax:0.4 MHzBase Number Matches:1

CAT9552HV6I-G 数据手册

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CAT9552  
FUNCTIONAL DESCRIPTION  
The CAT9552 is a 16-channel I/O bus expander that  
provides a pair of programmable LED blinkers,  
controlled through an I2C compatible serial interface.  
SDA when SCL is HIGH. The CAT9552 monitors the  
SDA and SCL lines and will not respond until this  
condition is met.  
CAT9552 supports the I2C Bus data transmission  
protocol. This Inter-Integrated Circuit Bus protocol  
defines any device that sends data to the bus to be a  
transmitter and any device receiving data to be a  
receiver. The transfer is controlled by the Master  
device which generates the serial clock and all  
START and STOP conditions for bus access. The  
CAT9552 operates as a Slave device. Both the  
Master device and Slave device can operate as either  
transmitter or receiver, but the Master device controls  
which mode is activated.  
A LOW to HIGH transition of SDA when SCL is HIGH  
determines the STOP condition. All operations must  
end with a STOP condition.  
Device Addressing  
After the bus Master sends a START condition, a  
slave address byte is required to enable the CAT9552  
for a read or write operation. The four most significant  
bits of the slave address are fixed as binary 1100  
(Figure 3). The CAT9552 uses the next three bits as  
address bits.  
I2C Bus Protocol  
The features of the I2C bus protocol are defined as  
follows:  
The address bits A2, A1 and A0 are used to select  
which device is accessed from maximum eight  
devices on the same bus. These bits must compare to  
their hardwired input pins. The 8th bit following the 7-  
bit slave address is the R/W bit that specifies whether  
a read or write operation is to be performed. When  
this bit is set to “1”, a read operation is initiated, and  
when set to “0”, a write operation is selected.  
(1) Data transfer may be initiated only when the bus  
is not busy.  
(2) During a data transfer, the data line must remain  
stable whenever the clock line is high. Any  
changes in the data line while the clock line is  
high will be interpreted as a START or STOP  
condition (Figure 2).  
Following the START condition and the slave address  
byte, the CAT9552 monitors the bus and responds  
with an acknowledge (on the SDA line) when its  
address matches the transmitted slave address. The  
CAT9552 then performs a read or a write operation  
depending on the state of the R/W bit.  
START and STOP Conditions  
The START Condition precedes all commands to the  
device, and is defined as a HIGH to LOW transition of  
SDA  
SCL  
START CONDITION  
STOP CONDITION  
Figure 2. Start/Stop Timing  
SLAVE ADDRESS  
1
1
0
0
A2  
A1  
A0 R/W  
FIXED  
PROGRAMMABLE  
HARDWARE  
SELECTABLE  
Figure 3. CAT9552 Slave Address  
© 2010 SCILLC. All rights reserved  
Characteristics subject to change without notice  
7
Doc. No. MD-9005 Rev D  

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