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CAT34C02HU4IGT4A PDF预览

CAT34C02HU4IGT4A

更新时间： 2024-02-15 05:58:40
品牌 Logo 应用领域
安森美 - ONSEMI 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟双倍数据速率光电二极管内存集成电路
页数 文件大小 规格书
17页 229K
描述
EEPROM Serial 2-Kb I2C forDDR2 DIMM SPD

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CAT34C02HU4IGT4A 技术参数

是否无铅： 不含铅生命周期：Active
包装说明：UDFN-8针数：8
Reach Compliance Code：compliantFactory Lead Time：1 week
风险等级：1.21其他特性：100 YEAR DATA RETENTION
最大时钟频率 (fCLK)：0.4 MHz数据保留时间-最小值：100
耐久性：1000000 Write/Erase CyclesI2C控制字节：1010DDDR
JESD-30 代码：R-PDSO-N8JESD-609代码：e4
长度：3 mm内存密度：256 bit
内存集成电路类型：EEPROM内存宽度：16
湿度敏感等级：1功能数量：1
端子数量：8字数：16 words
字数代码：16工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：16X16封装主体材料：PLASTIC/EPOXY
封装代码：HVSON封装等效代码：SOLCC8,.11,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
并行/串行：SERIAL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.8/5 V认证状态：Not Qualified
座面最大高度：0.55 mm串行总线类型：I2C
最大待机电流：0.000001 A子类别：EEPROMs
最大压摆率：0.002 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：2 mm最长写入周期时间 (tWC)：5 ms
写保护：HARDWARE/SOFTWAREBase Number Matches：1

CAT34C02HU4IGT4A 数据手册

 浏览型号CAT34C02HU4IGT4A的Datasheet PDF文件第5页浏览型号CAT34C02HU4IGT4A的Datasheet PDF文件第6页浏览型号CAT34C02HU4IGT4A的Datasheet PDF文件第7页浏览型号CAT34C02HU4IGT4A的Datasheet PDF文件第9页浏览型号CAT34C02HU4IGT4A的Datasheet PDF文件第10页浏览型号CAT34C02HU4IGT4A的Datasheet PDF文件第11页 
CAT34C02  
Software Write Protection  
is set and with ACK if the flag is not set. Therefore, the  
Master can immediately follow up with a STOP, as there is  
no meaningful data following the ACK interval (Figure 15).  
The lower half of memory (first 128 bytes) can be  
protected against Write requests by setting one of two  
Software Write Protection (SWP) flags.  
The Permanent Software Write Protection (PSWP) flag  
can be set or read while all address pins are at regular CMOS  
Hardware Write Protection  
With the WP pin held HIGH, the entire memory, as well  
as the SWP flags are protected against Write operations, see  
Memory Protection Map below. If the WP pin is left floating  
or is grounded, it has no impact on the operation of the  
CAT34C02.  
The state of the WP pin is strobed on the last falling edge  
of SCL immediately preceding the first data byte (Figure 9).  
If the WP pin is HIGH during the strobe interval, the  
CAT34C02 will not acknowledge the data byte and the Write  
request will be rejected.  
levels (GND or V ), whereas the very high voltage V  
CC  
HV  
must be present on address pin A to set, clear or read the  
0
Reversible Software Write Protection (RSWP) flag. The  
D.C. OPERATING CONDITIONS for RSWP operations  
are shown in Table 8.  
The SWP commands are listed in Table 9. All commands  
are preceded by a START and terminated with a STOP,  
following the ACK or NoACK from the CAT34C02. All  
SWP related Slave addresses use the pre−amble: 0110 (6h),  
instead of the regular 1010 (Ah) used for memory access.  
For PSWP commands, the three address pins can be at any  
logic level, whereas for RSWP commands the address pins  
FFH  
must be at pre−assigned logic levels. V is interpreted as  
HV  
Hardware Write Protectable  
(by connecting WP pin to  
logic ‘1’. The V condition must be established on pin A  
HV  
0
before the START and maintained just beyond the STOP.  
Otherwise an RSWP request could be interpreted by the  
CAT34C02 as a PSWP request.  
V
CC  
)
7FH  
00H  
2
Software Write Protectable  
(by setting the write  
protect flags)  
The SWP Slave addresses follow the standard I C  
convention, i.e. to read the state of the SWP flag, the LSB of  
the Slave address must be ‘1’, and to set or clear a flag, it  
must be ‘0’. For Write commands a dummy byte address and  
dummy data byte must be provided (Figure 14). In contrast  
to a regular memory Read, a SWP Read does not return Data.  
Instead the CAT34C02 will respond with NoACK if the flag  
Figure 13. Memory Protection Map  
Table 8. RSWP D.C. OPERATING CONDITIONS (Note 11)  
Symbol  
Parameter  
A Overdrive (V − V  
Test Conditions  
Min  
Max  
Units  
V
DV  
)
1.7 V < V < 3.6 V  
4.8  
HV  
0
HV  
CC  
CC  
I
A High Voltage Detector Current  
0.1  
10  
1
mA  
V
HVD  
0
V
A Very High Voltage  
0
7
HV  
I
A Input Current @ V  
mA  
HV  
0
HV  
11. To prevent damaging the CAT34C02 while applying V , it is strongly recommended to limit the power delivered to pin A , by inserting a series  
HV  
0
resistor (> 1.5 kW) between the supply and the input pin. The resistance is only limited by the combination of V and maximum I  
. While  
HV  
HVD  
the resistor can be omitted if V is clamped well below 10 V, it nevertheless provides simple protection against EOS events.  
HV  
As an example: V = 1.7 V, V = 8 V, 1.5 kW < R < 15 kW.  
CC  
HV  
S
www.onsemi.com  
8
 
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