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CAT25C32Y14I-1.8 PDF预览

CAT25C32Y14I-1.8

更新时间： 2024-11-20 05:35:07
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
11页 403K
描述
CAT25C32Y14I-1.8

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中文翻译

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CAT25C32Y14I-1.8 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknown风险等级：5.84

CAT25C32Y14I-1.8 数据手册

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CAT25C32/64  
32K/64K-Bit SPI Serial CMOS EEPROM  
FEATURES  
■ 1,000,000 program/erase cycles  
■ 100 year data tetention  
■ 10 MHz SPI compatible  
■ 1.8 to 6.0 volt operation  
■ Hardware and software protection  
■ Low power CMOS technology  
■ SPI modes (0,0 &1,1)  
■ Self-timed write cycle  
■ 8-pin DIP/SOIC and 14-pin TSSOP  
■ 64-Byte page write buffer  
■ Block write protection  
■ Commercial, industrial and automotive  
– Protect 1/4, 1/2 or all of EEPROM array  
temperature ranges  
DESCRIPTION  
required to access the device. The HOLD pin may be  
used to suspend any serial communication without  
resetting the serial sequence. The CAT25C32/64 is  
designed with software and hardware write protection  
features including Block write protection. The device is  
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and  
20-pin TSSOP packages.  
The CAT25C32/64 is a 32K/64K-Bit SPI Serial CMOS  
EEPROM internally organized as 4Kx8/8Kx8 bits.  
Catalyst’s advanced CMOS Technology substantially  
reduces device power requirements. The CAT25C32/  
64 features a 64-byte page write buffer. The device  
operates via the SPI bus serial interface and is enabled  
thoughaChipSelect(CS). InadditiontotheChipSelect,  
the clock input (SCK), data in (SI) and data out (SO) are  
PIN CONFIGURATION  
DIP Package (P, L, GL)  
SOIC Package (S, V, GV)  
TSSOP Package (U14, Y14)  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
8
VCC  
HOLD  
NC  
NC  
NC  
V
CS  
SO  
WP  
CS  
SO  
NC  
NC  
NC  
WP  
CS  
SO  
CC  
CC  
HOLD  
SCK  
SI  
HOLD  
SCK  
SI  
WP  
V
V
SS  
SS  
SCK  
SI  
V
SS  
BLOCK DIAGRAM  
SENSE AMPS  
SHIFT REGISTERS  
PIN FUNCTIONS  
COLUMN  
DECODERS  
WORD ADDRESS  
BUFFERS  
Pin Name  
Function  
SO  
Serial Data Output  
Serial Clock  
SO  
SI  
I/O  
CONTROL  
SCK  
WP  
VCC  
VSS  
CS  
E2PROM  
ARRAY  
CS  
SPI  
CONTROL  
LOGIC  
XDEC  
Write Protect  
WP  
HOLD  
SCK  
+1.8V to +6.0V Power Supply  
Ground  
BLOCK  
PROTECT  
LOGIC  
Chip Select  
DATA IN  
STORAGE  
SI  
Serial Data Input  
Suspends Serial Input  
HOLD  
HIGH VOLTAGE/  
TIMING CONTROL  
NC  
No Connect  
STATUS  
REGISTER  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1001, Rev. J  
1
1234567...11

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