CAT25C11/03/05/09/17
and forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25C11/03/
05/09/17 draws ZERO current in the Standby mode. A
high to low transition on CS is required prior to any
sequence being initiated. A low to high transition on CS
after a valid write sequence is what initiates an internal
write cycle.
SPI modes (0,0 & 1,1).
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
25C11/03/05/09/17. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK for SPI modes (0,0 & 1,1).
WP: Write Protect
WPistheWriteProtectpin.TheWriteProtectpinwillallow
normalread/writeoperationswhenheldhigh.WhenWPis
tiedlowandtheWPENbitinthestatusregisterissetto"1",
all write operations to the status register are inhibited. WP
going low while CS is still low will interrupt a write to the
status register. If the internal write cycle as already been
initiated, WP going low will have no effect on any write
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C11/
03/05/09/17 and CS high disables the CAT25C11/03/05/
09/17. CShightakestheSOoutputpintohighimpedance
BYTE ADDRESS
Device
Address Significant Bits
Address Don't Care Bits
# Address Clock Pulse
CAT25C11
CAT25C03
CAT25C05
CAT25C09
CAT25C17
A6 - A0
A7
—
8
8
A7 - A0
A7 - A0 (A8 = X bit from Opcode)
A9 - A0
—
8
A15 - A10
A15 - A11
16
16
A10 - A0
STATUS REGISTER
7
6
1
5
1
4
3
2
1
0
WPEN
BP2
BP1
BP0
WEL
RDY
MEMORY PROTECTION
25C11
25C03
25C05
25C09
25C17
BP2
0
BP1
0
BP0
0
Q1
Q2
Q3
Q4
H1
P0
Pn
00-1F
20-3F
40-5F
60-7F
00-3F
00-0F
70-7F
00-3F 000-07F 000-0FF 000-1FF
40-7F 080-0FF 100-1FF 200-3FF
80-BF 100-17F 200-2FF 400-5FF
C0-FF 180-1FF 300-3FF 600-7FF
00-7F 000-0FF 000-1FF 000-3FF
00-0F 000-00F 000-01F 000-01F
F0-FF 1F0-1FF 3E0-3FF 7E0-7FF
Non-Protection
Q1 Protected
Q2 Protected
Q3 Protected
Q4 Protected
H1 Protected
P0 Protected
Pn Protected
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
WEL
0
X
0
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
0
1
1
X
X
X
1
0
1
0
1
Low
Low
High
High
Protected
Protected
Protected
Writable
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1017, Rev. L
5