5秒后页面跳转
CAT25C02VI-1.8TE13 PDF预览

CAT25C02VI-1.8TE13

更新时间: 2024-01-02 05:17:37
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
15页 375K
描述
1K/2K/4K SPI Serial CMOS EEPROM

CAT25C02VI-1.8TE13 数据手册

 浏览型号CAT25C02VI-1.8TE13的Datasheet PDF文件第1页浏览型号CAT25C02VI-1.8TE13的Datasheet PDF文件第2页浏览型号CAT25C02VI-1.8TE13的Datasheet PDF文件第4页浏览型号CAT25C02VI-1.8TE13的Datasheet PDF文件第5页浏览型号CAT25C02VI-1.8TE13的Datasheet PDF文件第6页浏览型号CAT25C02VI-1.8TE13的Datasheet PDF文件第7页 
CAT25C01, CAT25C02, CAT25C04  
A.C. CHARACTERISTICS  
SYMBOL PARAMETER  
CAT25CXX-1.8  
1.8V-5.5V  
CAT25CXX  
2.5V-5.5V 4.5V-5.5V  
Test  
Min.  
50  
Max. Min.  
Max. Min. Max.  
UNITS Conditions  
tSU  
tH  
Data Setup Time  
Data Hold Time  
20  
20  
75  
75  
DC  
20  
20  
40  
40  
ns  
ns  
50  
tWH  
tWL  
fSCK  
tLZ  
SCK High Time  
250  
250  
DC  
ns  
SCK Low Time  
ns  
Clock Frequency  
HOLD to Output Low Z  
Input Rise Time  
1
50  
2
5
50  
2
DC  
10  
50  
2
MHz  
ns  
(1)  
tRI  
µs  
(1)  
tFI  
Input Fall Time  
2
2
2
µs  
tHD  
tCD  
HOLD Setup Time  
HOLD Hold Time  
Write Cycle Time  
Output Valid from Clock Low  
Output Hold Time  
Output Disable Time  
HOLD to Output High Z  
CS High Time  
100  
100  
40  
40  
40  
40  
ns  
ns  
(4)  
CL = 50pF  
(note 2)  
tWC  
tV  
5
5
5
ms  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
250  
75  
40  
tHO  
0
0
0
tDIS  
tHZ  
250  
150  
75  
50  
75  
50  
tCS  
500  
500  
500  
150  
150  
100  
100  
100  
50  
100  
100  
100  
50  
tCSS  
tCSH  
tWPS  
tWPH  
CS Setup Time  
CS Hold Time  
WP Setup Time  
WP Hold Time  
50  
50  
(1)(3)  
Power-Up Timing  
Symbol  
tPUR  
Parameter  
Max.  
Units  
Power-up to Read Operation  
Power-up to Write Operation  
1
1
ms  
ms  
tPUW  
NOTE:  
(1) This parameter is tested initially and after a design or process change that affects the parameter.  
(2) AC Test Conditions:  
Input Pulse Voltages: 0.3V to 0.7V  
CC  
CC  
Input rise and fall times: 10ns  
Input and output reference voltages: 0.5V  
CC  
Output load: current source I max/I max; C =50pF  
OL  
OH  
L
(3)  
(4)  
t
t
and t  
are the delays required from the time V is stable until the specified operation can be initiated.  
PUR  
WC  
PUW CC  
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1105, Rev. B  
3

与CAT25C02VI-1.8TE13相关器件

型号 品牌 描述 获取价格 数据表
CAT25C02VITE13 CATALYST 1K/2K/4K SPI Serial CMOS EEPROM

获取价格

CAT25C02VI-TE13 ETC EEPROM

获取价格

CAT25C02V-TE13 ETC EEPROM

获取价格

CAT25C02X CATALYST Supervisory Circuits with SPI Serial E2PROM, Precision Reset Controller and Watchdog Timer

获取价格

CAT25C02X-1.8TE13 CATALYST EEPROM

获取价格

CAT25C02XA-1.8TE13 ETC EEPROM

获取价格