CAT24CXX1/XX2
Advanced
Immediate/Current Address Read
The CAT24CXXX’s address counter contains the ad-
dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac-
cess data from address N+1. If N=E (where E= 255 for
24C021/022, E=511 for 24C041/042, E=1023 for
24C081/082 and E=2047 for 24C161/162) then the
counter will ‘wrap around’ to address 0 and continue to
clock out data. After the CAT24CXXX receives its slave
address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an ac-
knowledge, but will generate a STOP condition.
doesnotsendanacknowledgebutwillgenerateaSTOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24CXXX sends the initial 8-bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24CXXX will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operationwillterminatewhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
Selective/Random Read
The data being transmitted from CAT24CXXX is output-
ted sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24CXXX address bits
so that the entire memory array can be read during one
operation. If more than E (where E= 255 for 24C021/
022, E=511 for 24C041/042, E=1023 for 24C081/082
and E=2047 for 24C161/162) bytes are read out, the
counter will ‘wrap around’ and continue to clock out data
bytes.
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24CXXX acknowledges, the
MasterdevicesendstheSTARTconditionandtheslave
address again, this time with the R/W bit set to one.
The CAT24CXXX then responds with its acknowledge
and sends the 8-bit byte requested. The master device
Figure 10. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
24C1601Fig.9
Figure 11. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
24C1601Fig.10
Doc. No. 25079-00 1/98 M-1
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