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CAT24C161JI-25 PDF预览

CAT24C161JI-25

更新时间： 2024-02-22 03:25:44
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
12页 73K
描述
EEPROM, 2KX8, Serial, CMOS, PDSO8

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CAT24C161JI-25 技术参数

是否Rohs认证：不符合生命周期：Obsolete
包装说明：SOP, SOP8,.25Reach Compliance Code：unknown
风险等级：5.92Is Samacsys：N
数据保留时间-最小值：100耐久性：1000000 Write/Erase Cycles
I2C控制字节：1010MMMRJESD-30 代码：R-PDSO-G8
JESD-609代码：e0内存密度：16384 bit
内存集成电路类型：EEPROM内存宽度：8
端子数量：8字数：2048 words
字数代码：2000最高工作温度：85 °C
最低工作温度：-40 °C组织：2KX8
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：SERIAL
电源：3 V认证状态：Not Qualified
串行总线类型：I2C子类别：EEPROMs
最大压摆率：0.003 mA标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL写保护：HARDWARE
Base Number Matches：1

CAT24C161JI-25 数据手册

 浏览型号CAT24C161JI-25的Datasheet PDF文件第6页浏览型号CAT24C161JI-25的Datasheet PDF文件第7页浏览型号CAT24C161JI-25的Datasheet PDF文件第8页浏览型号CAT24C161JI-25的Datasheet PDF文件第9页浏览型号CAT24C161JI-25的Datasheet PDF文件第11页浏览型号CAT24C161JI-25的Datasheet PDF文件第12页 
CAT24CXX1/XX2  
Advanced Information  
Immediate/Current Address Read  
The CAT24CXXX’s address counter contains the ad-  
dress of the last byte accessed, incremented by one. In  
other words, if the last READ or WRITE access was to  
address N, the READ immediately following would ac-  
cess data from address N+1. If N=E (where E= 255 for  
24C021/022, E=511 for 24C041/042, E=1023 for  
24C081/082 and E=2047 for 24C161/162) then the  
counter will ‘wrap around’ to address 0 and continue to  
clock out data. After the CAT24CXXX receives its slave  
address information (with the R/W bit set to one), it  
issues an acknowledge, then transmits the 8-bit byte  
requested. The master device does not send an ac-  
knowledge, but will generate a STOP condition.  
doesnotsendanacknowledgebutwillgenerateaSTOP  
condition.  
Sequential Read  
The Sequential READ operation can be initiated by  
either the Immediate Address READ or Selective READ  
operations. After the CAT24CXXX sends the initial 8-bit  
byte requested, the Master will respond with an  
acknowledge which tells the device it requires more  
data. The CAT24CXXX will continue to output an 8-bit  
byte for each acknowledge sent by the Master. The  
operationwillterminatewhentheMasterfailstorespond  
with an acknowledge, thus sending the STOP condition.  
Selective/Random Read  
The data being transmitted from CAT24CXXX is output-  
ted sequentially with data from address N followed by  
data from address N+1. The READ operation address  
counter increments all of the CAT24CXXX address bits  
so that the entire memory array can be read during one  
operation. If more than E (where E= 255 for 24C021/  
022, E=511 for 24C041/042, E=1023 for 24C081/082  
and E=2047 for 24C161/162) bytes are read out, the  
counter will ‘wrap around’ and continue to clock out data  
bytes.  
Selective/Random READ operations allow the Master  
device to select at random any memory location for a  
READ operation. The Master device first performs a  
‘dummy’ write operation by sending the START condi-  
tion, slave address and byte addresses of the location it  
wishes to read. After CAT24CXXX acknowledges, the  
MasterdevicesendstheSTARTconditionandtheslave  
address again, this time with the R/W bit set to one.  
The CAT24CXXX then responds with its acknowledge  
and sends the 8-bit byte requested. The master device  
Figure 10. Selective Read Timing  
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS (n)  
SLAVE  
ADDRESS  
SDA LINE  
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n  
A
C
K
24C1601Fig.9  
Figure 11. Sequential Read Timing  
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
DATA n  
DATA n+1  
DATA n+2  
DATA n+x  
SDA LINE  
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
24C1601Fig.10  
Doc. No. 25079-00 8/99 M-1  
10  
1...789101112

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