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CAT24C083JA-45TE13

更新时间： 2024-02-17 09:35:43
品牌 Logo 应用领域
CATALYST 监控控制器可编程只读存储器
页数 文件大小 规格书
12页 89K
描述
Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

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CAT24C083JA-45TE13 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：8Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.92可调阈值：YES
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-PDSO-G8
JESD-609代码：e0长度：4.9 mm
信道数量：1功能数量：1
端子数量：8最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

CAT24C083JA-45TE13 数据手册

 浏览型号CAT24C083JA-45TE13的Datasheet PDF文件第2页浏览型号CAT24C083JA-45TE13的Datasheet PDF文件第3页浏览型号CAT24C083JA-45TE13的Datasheet PDF文件第4页浏览型号CAT24C083JA-45TE13的Datasheet PDF文件第6页浏览型号CAT24C083JA-45TE13的Datasheet PDF文件第7页浏览型号CAT24C083JA-45TE13的Datasheet PDF文件第8页 
CAT24C163/083/043/023  
Advanced  
PIN DESCRIPTIONS  
with open drain RESET outputs. During power-up, the  
RESET outputs remain active until VCC reaches the  
VTH threshold and will continue driving the outputs for  
approximately 200ms (tPURST) after reaching VTH. After  
the tPURST timeout interval, the device will cease to drive  
resetoutputs.Atthispointtheresetoutputswillbepulled  
upordownbytheirrespectivepullup/pulldowndevices.  
During power-down, the RESET outputs will begin driv-  
ing active when VCC falls below VTH. The RESET  
outputs will be valid so long as VCC is >1.0V (VRVALID).  
WDI: WATCHDOG INPUT  
If there is no transition on the WDI for more than 1.6  
seconds, the watchdog timer times out.  
WP: WRITE PROTECT  
If the pin is tied to VCC the entire memory array becomes  
WriteProtected(READonly). WhenthepinistiedtoVSS  
or left floating normal read/write operations are allowed  
to the device.  
The RESET pins are I/Os; therefore, the CAT24CXXX  
can act as a signal conditioning circuit for an externally  
applied reset. The inputs are level triggered; that is, the  
RESET input in the 24CXXX will initiate a reset timeout  
after detecting a high and the RESET input in the  
24CXXXwillinitiatearesettimeoutafterdetectingalow.  
SCL: SERIAL CLOCK  
The serial clock input clocks all data transferred into or  
out of the device.  
RESET/RESET: RESET I/O  
These are open drain pins and can be used as reset  
triggerinputs. Byforcingaresetconditiononthepinsthe  
device will initiate and maintain a reset condition for  
approximately 200ms. RESET pin must be connected  
through a pull-down and RESET pin must be connected  
through a pull-up device.  
Watchdog Timer  
The Watchdog Timer provides an independent protec-  
tion for microcontrollers. During a system failure, the  
CAT24CXXX will respond with a reset signal after a  
time-outintervalof1.6secondsforalackofactivity. The  
24CXX3 is designed with a WDI input pin for the Watch-  
dogTimerfunction. Forthe24CXX3,ifthemicrocontroller  
doesnot toggletheWDIinputpinwithin1.6seconds,the  
Watchdog Timer times out. This will generate a reset  
condition on reset outputs. The Watchdog Timer is  
cleared by any transition on WDI.  
SDA: SERIAL DATA/ADDRESS  
The bidirectional serial data/address pin is used to  
transfer all data into and out of the device. The SDA pin  
is an open drain output and can be wire-ORed with other  
open drain or open collector outputs.  
DEVICE OPERATION  
Reset Controller Description  
As long as the reset signal is asserted, the Watchdog  
Timer will not count and will stay cleared.  
The CAT24CXXX provides a precision RESET control-  
ler that ensures correct system operation during brown-  
out and power up/down conditions. It is configured  
t
Figure 1. RESET Output Timing  
GLITCH  
V
TH  
V
RVALID  
V
CC  
t
RPD  
t
t
PURST  
PURST  
RESET  
t
RPD  
RESET  
Doc. No. 25080-00 3/98 M-1  
5
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