Datasheet > CAT24C041PA-28TE13

CAT24C041PA-28TE13

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
CATALYST		监控控制器可编程只读存储器
页数	文件大小	规格书
12页	89K
描述
Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

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Advanced

CAT24CXX1/XX2

Acknowledge Polling

protected and becomes read only. The CAT24CXXX

will accept both slave and byte addresses, but the

memory location accessed is protected from program-

ming by the device's failure to send an acknowledge

after the first byte of data is received.

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is

issued to indicate the end of the host’s write operation,

CAT24CXXX initiates the internal write cycle. ACK poll-

ing can be initiated immediately. This involves issuing

the start condition followed by the slave address for a

writeoperation. IfCAT24CXXXisstillbusywiththewrite

operation, no ACK will be returned. If

CAT24CXXX has completed the write operation, an

ACK will be returned and the host can then proceed with

the next read or write operation.

READ OPERATIONS

The READ operation for the CAT24CXXX is initiated in

the same manner as the write operation with one excep-

tion, that R/W bit is set to one. Three different READ

operations are possible: Immediate/Current Address

READ,Selective/Random READandSequential READ.

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent programming of the memory array.

If the WP pin is tied to V_CC, the entire memory array is

Figure 9. Immediate Address Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

SDA LINE

DATA

SCL

SDA

8TH BIT

DATA OUT

NO ACK

STOP

24C1601Fig.8

Doc. No. 25079-00 1/98 M-1

1...6 7 8910 11 12

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