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CAT24C041J-42 PDF预览

CAT24C041J-42

更新时间: 2024-01-24 05:38:11
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
12页 73K
描述
EEPROM, 512X8, Serial, CMOS, PDSO8

CAT24C041J-42 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP8,.25Reach Compliance Code:unknown
风险等级:5.92数据保留时间-最小值:100
耐久性:1000000 Write/Erase CyclesI2C控制字节:1010XXMR
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
内存密度:4096 bit内存集成电路类型:EEPROM
内存宽度:8端子数量:8
字数:512 words字数代码:512
最高工作温度:70 °C最低工作温度:
组织:512X8封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:SERIAL电源:5 V
认证状态:Not Qualified串行总线类型:I2C
最大待机电流:0.00005 A子类别:EEPROMs
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
写保护:HARDWAREBase Number Matches:1

CAT24C041J-42 数据手册

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Advanced Information  
PIN DESCRIPTIONS  
CAT24CXX1/XX2  
WP: WRITE PROTECT  
VTH threshold and will continue driving the outputs for  
approximately 200ms (tPURST) after reaching VTH. After  
the tPURST timeout interval, the device will cease to drive  
reset outputs. At this point the reset outputs will be  
pulled up or down by their respective pull up/pull down  
devices. During power-down, the RESET outputs will  
begin driving active when VCC falls below VTH. The  
RESET outputs will be valid so long as VCC is >1.0V  
(VRVALID).  
If the pin is tied to VCC the entire memory array becomes  
WriteProtected(READonly). WhenthepinistiedtoVSS  
or left floating normal read/write operations are allowed  
to the device.  
SCL: SERIAL CLOCK  
The serial clock input clocks all data transferred into or  
out of the device.  
RESET/RESET: RESET I/O  
The RESET pins are I/Os; therefore, the CAT24CXXX  
can act as a signal conditioning circuit for an externally  
applied reset. The inputs are edge triggered; that is, the  
RESET input in the 24CXXX will initiate a reset timeout  
after detecting a low to high transition and the RESET  
input in the 24CXXX will initiate a reset timeout after  
detecting a high to low transition.  
These are open drain pins and can be used as reset  
triggerinputs. Byforcingaresetconditiononthepinsthe  
device will initiate and maintain a reset condition for  
approximately 200ms. RESET pin must be connected  
through a pull-down and RESET pin must be connected  
through a pull-up device.  
Watchdog Timer  
SDA: SERIAL DATA/ADDRESS  
The bidirectional serial data/address pin is used to  
transfer all data into and out of the device. The SDA pin  
is an open drain output and can be wire-ORed with other  
opendrainoropencollectoroutputs. Inthe24CXX1, the  
SDA line is also used as the Watchdog Timer Monitor.  
The Watchdog Timer provides an independent protec-  
tion for microcontrollers. During a system failure, the  
CAT24CXX1willrespondwitharesetsignalafteratime-  
out interval of 1.6 seconds for lack of activity. 24CXX1  
isdesignedwiththeWatchdogTimerfeatureontheSDA  
input. For the 24CXX1, if the microcontroller does not  
toggle the SDA input pin within 1.6 seconds the Watch-  
dog Timer times out. This will generate a reset condition  
onresetoutputs. The WatchdogTimerisclearedbyany  
transition on SDA.  
DEVICE OPERATION  
Reset Controller Description  
The CAT24CXXX provides a precision RESET control-  
ler that ensures correct system operation during brown-  
out and power-up/down conditions. It is configured  
with open drain RESET outputs. During power-up, the  
RESET outputs remain active until VCC reaches the  
As long as the reset signal is asserted, the Watchdog  
Timer will not count and will stay cleared. 24CXX2 does  
not feature the Watchdog Timer function.  
Figure 1. RESET Output Timing  
tGLITCH  
VTH  
V
RVALID  
VCC  
tRPD  
tPURST  
tPURST  
RESET  
tRPD  
RESET  
Doc. No. 25079-00 8/99 M-1  
5

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