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CAT24C01BR-1.8TE13REVA PDF预览

CAT24C01BR-1.8TE13REVA

更新时间: 2024-11-19 14:33:03
品牌 Logo 应用领域
CATALYST 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟光电二极管内存集成电路
页数 文件大小 规格书
8页 611K
描述
EEPROM, 128X8, Serial, CMOS, PDSO8, MSOP-8

CAT24C01BR-1.8TE13REVA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:MSOP包装说明:TSSOP,
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.72最大时钟频率 (fCLK):0.4 MHz
JESD-30 代码:S-PDSO-G8JESD-609代码:e0
长度:3 mm内存密度:1024 bit
内存集成电路类型:EEPROM内存宽度:8
功能数量:1端子数量:8
字数:128 words字数代码:128
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:128X8
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行:SERIAL峰值回流温度(摄氏度):240
认证状态:Not Qualified座面最大高度:1.1 mm
串行总线类型:I2C最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):1.8 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mm最长写入周期时间 (tWC):10 ms
Base Number Matches:1

CAT24C01BR-1.8TE13REVA 数据手册

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CAT24C01B  
1K-Bit Serial EEPROM  
FEATURES  
I 1,000,000 Program/Erase Cycles  
I 100 Year Data Retention  
I 2-Wire Serial Interface  
I 1.8 to 6.0Volt Operation  
I 8-pin DIP, 8-pin SOIC, 8 pin TSSOP or 8-pin MSOP  
I Low Power CMOS Technology  
I 4-Byte Page Write Buffer  
I Commercial, Industrial and Automotive  
Temperature Ranges  
I Self-Timed Write Cycle with Auto-Clear  
I "Green" Package Options Available  
DESCRIPTION  
4-byte page write buffer. The device operates via a 2-  
wire serial interface and is available in 8-pin DIP, 8-pin  
SOIC, 8-pin TSSOP or 8-pin MSOP.  
The CAT24C01B is a 1K-bit Serial CMOS EEPROM  
internallyorganizedas128wordsof8bitseach.Catalyst’s  
advanced CMOS technology substantially reduces de-  
vice power requirements. The CAT24C01B features a  
PIN CONFIGURATION  
BLOCK DIAGRAM  
SOIC Package (J, W, GW)  
DIP Package (P, L, GL)  
EXTERNAL LOAD  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
NC  
NC  
NC  
SENSE AMPS  
SHIFT REGISTERS  
CC  
NC  
NC  
NC  
V
CC  
TEST  
D
OUT  
TEST  
ACK  
SCL  
SCL  
V
V
CC  
SS  
V
SDA  
V
SS  
SS  
SDA  
WORD ADDRESS  
BUFFERS  
COLUMN  
DECODERS  
START/STOP  
SDA  
LOGIC  
MSOP Package (R, Z, GZ)  
TSSOP Package (U, Y, GY)  
1
2
3
4
8
7
6
5
V
1
2
3
4
8
7
6
5
NC  
NC  
NC  
CC  
NC  
NC  
NC  
V
CC  
TEST  
XDEC  
EEPROM  
TEST  
SCL  
CONTROL  
LOGIC  
SCL  
V
SDA  
V
SS  
SS  
SDA  
DATA IN STORAGE  
PIN FUNCTIONS  
Pin Name  
Function  
HIGH VOLTAGE/  
TIMING CONTROL  
NC  
No Connect  
SDA  
SCL  
VCC  
VSS  
Serial Data/Address  
Serial Clock  
SCL  
STATE COUNTERS  
+1.8V to +6.0V Power Supply  
Ground  
TEST  
Test Input (GND, VCC or  
Floating)  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1081, Rev. E  
1

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