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CA3146M

更新时间： 2024-01-02 23:46:06
品牌 Logo 应用领域
英特矽尔 - INTERSIL 晶体晶体管开关光电二极管
页数 文件大小 规格书
12页 124K
描述
High-Voltage Transistor Arrays

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CA3146M 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：SMALL OUTLINE, R-PDSO-G14Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8541.21.00.75
风险等级：5.7其他特性：LOW NOISE
最大集电极电流 (IC)：0.05 A集电极-发射极最大电压：30 V
配置：COMPLEX最小直流电流增益 (hFE)：30
最高频带：VERY HIGH FREQUENCY BANDJEDEC-95代码：MS-012AB
JESD-30 代码：R-PDSO-G14JESD-609代码：e0
元件数量：5端子数量：14
最高工作温度：150 °C封装主体材料：PLASTIC/EPOXY
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
极性/信道类型：NPN认证状态：Not Qualified
表面贴装：YES端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子位置：DUAL
晶体管应用：SWITCHING晶体管元件材料：SILICON
标称过渡频率 (fT)：500 MHzBase Number Matches：1

CA3146M 数据手册

 浏览型号CA3146M的Datasheet PDF文件第6页浏览型号CA3146M的Datasheet PDF文件第7页浏览型号CA3146M的Datasheet PDF文件第8页浏览型号CA3146M的Datasheet PDF文件第9页浏览型号CA3146M的Datasheet PDF文件第10页浏览型号CA3146M的Datasheet PDF文件第11页 
CA3146, CA3146A, CA3183, CA3183A  
Small Outline Plastic Packages (SOIC)  
M16.15 (JEDEC MS-012-AC ISSUE C)  
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC  
PACKAGE  
N
INDEX  
AREA  
0.25(0.010)  
M
B M  
H
E
INCHES  
MILLIMETERS  
-B-  
SYMBOL  
MIN  
MAX  
0.0688  
0.0098  
0.020  
MIN  
1.35  
0.10  
0.33  
0.19  
9.80  
3.80  
MAX  
1.75  
0.25  
0.51  
0.25  
10.00  
4.00  
NOTES  
A
A1  
B
C
D
E
e
0.0532  
0.0040  
0.013  
-
1
2
3
L
-
SEATING PLANE  
A
9
-A-  
0.0075  
0.3859  
0.1497  
0.0098  
0.3937  
0.1574  
-
o
h x 45  
D
3
4
-C-  
α
0.050 BSC  
1.27 BSC  
-
e
A1  
C
H
h
0.2284  
0.0099  
0.016  
0.2440  
0.0196  
0.050  
5.80  
0.25  
0.40  
6.20  
0.50  
1.27  
-
B
0.10(0.004)  
5
0.25(0.010) M  
C
A M B S  
L
6
N
α
16  
16  
7
NOTES:  
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of  
Publication Number 95.  
Rev. 0 12/93  
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.  
3. Dimension “D” does not include mold flash, protrusions or gate burrs.  
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006  
inch) per side.  
4. Dimension “E” does not include interlead flash or protrusions. Interlead  
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.  
5. The chamfer on the body is optional. If it is not present, a visual index  
feature must be located within the crosshatched area.  
6. “L” is the length of terminal for soldering to a substrate.  
7. “N” is the number of terminal positions.  
8. Terminal numbers are shown for reference only.  
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above  
the seating plane, shall not exceed a maximum value of 0.61mm  
(0.024 inch).  
10. Controlling dimension: MILLIMETER. Converted inch dimensions are  
not necessarily exact.  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Mercure Center  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
Intersil (Taiwan) Ltd.  
7F-6, No. 101 Fu Hsing North Road  
Taipei, Taiwan  
Republic of China  
TEL: (886) 2 2716 9310  
FAX: (886) 2 2715 3029  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (321) 724-7000  
FAX: (321) 724-7240  
12  
1...9101112

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