Datasheet > C9817AYB

C9817AYB

更新时间： 2024-01-08 16:27:50

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管外围集成电路
页数	文件大小	规格书
19页	207K
描述
Processor Specific Clock Generator, CMOS, PDSO56, SSOP-56

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技术参数
数据手册

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C9817AYB 技术参数

生命周期：	Obsolete	零件包装代码：	SSOP
包装说明：	SSOP,	针数：	56
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.84
JESD-30 代码：	R-PDSO-G56	JESD-609代码：	e0
长度：	18.415 mm	端子数量：	56
封装主体材料：	PLASTIC/EPOXY	封装代码：	SSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
认证状态：	Not Qualified	座面最大高度：	2.794 mm
表面贴装：	YES	技术：	CMOS
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	DUAL
宽度：	7.5 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

C9817AYB 数据手册

+/+…when timing is critical

C9817

133 MHz I²C Clock Generator for mobile Pentium^®III / Rambus Systems

Preliminary

Power Management Function Table

CPU_stp#

PWRDN#

PCI_stp#

CPU

CPU/2 3V66

(0:2)

PCI(0:6)

PCI_F

48MHz/

REF(0:2)

IOAPIC

(0:1)

PLL1 PLL2

run

off

run

off

run

Table 2

2-Wire I²C Control Interface

The 2-wire control interface implements a write slave only interface according to Philips I2C specification. (see fig5). The

device cannot be read back. Sub-addressing is not supported, thus all preceding bytes must be sent in order to change

one of the control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. 100

Kbits/second (standard mode) data transfer is supported.

During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is

high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the

start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer

cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer

cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode .

The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on

the SDATA wire following reception of each byte.

ACK

SDATA IS OUTPUT PIN

COMMAND BYTE

(DON'TCARE)

SDATA IS INPUT PIN

SDATA

MSB

LSB

SCLK

START CONDITION

CONTINUED

ACK

COUNT BYTE

(DON'TCARE)

BYTE 0

(VALID DATA)

BYTE N (LAST

VALID DATA)

CONTINUED

STOP CONDITION

Fig.5

INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.

MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571

WWW.IMICORP.COM

Rev 1.0

11/1/1999

Page 6 of 19

1...3 4 567 8 9...19

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与C9817AYB相关器件

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C981U103MYVDAA7317	KEMET	Safety Standard Recognized, 900 Series, Radial Disc, Encapsulated, X1 400 VAC / Y1 250 VAC	获取价格
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C981U103MZVDAA7317	KEMET	Ceramic Capacitor, Multilayer, Ceramic, 20% +Tol, 20% -Tol, Y5V, -80/+30% TC, 0.01uF, Thro	获取价格
C981U103MZVDAAWL20	KEMET	Ceramic Capacitor, Multilayer, Ceramic, 20% +Tol, 20% -Tol, Y5V, -80/+30% TC, 0.01uF, Thro	获取价格

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