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C9817AYB

更新时间： 2024-02-17 19:39:53
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管外围集成电路
页数 文件大小 规格书
19页 207K
描述
Processor Specific Clock Generator, CMOS, PDSO56, SSOP-56

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C9817AYB 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：18.415 mm端子数量：56
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：2.794 mm
表面贴装：YES技术：CMOS
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
宽度：7.5 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

C9817AYB 数据手册

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+/+…when timing is critical  
C9817  
133 MHz I2C Clock Generator for mobile Pentium®III / Rambus Systems  
Preliminary  
Pin Description (Cont.)  
PIN No.  
Pin Name  
PWR  
VDD  
I/O TYPE  
O
Description  
3.3 V Fixed 66.6Mhz Hub-link clock outputs. Synchronous to  
CPU clocks.  
37,38,41  
3V66 (0,2)  
44  
VDDC  
VDDC/2  
VDDI  
O
O
O
2.5 V Host bus clock output. Programmable per Table1,  
page1.  
2.5 V DRCG clock output. Half CPU frequency and  
synchronous to CPU clock.  
2.5 V APIC clock outputs. Fixed at 16.67MHz and  
synchronous to CPU clock.  
No connect  
CPU  
50  
CPU/2  
IOAPIC(0,1)  
N/C  
53,55  
46, 48, 52  
PU = Internal 250K Pull-up  
Power Plane Distribution  
PIN No.  
Pin Name  
Power to pins  
2,3,4,6,7  
Description  
5
8
3.3 V Power Supply for reference output clocks and crystal circuitry.  
3.3V Analog Core Power Supply.  
VDDR  
VDD  
11,18,19,26  
10,12,13,16,17, 3.3V common power supply pin for PCI clocks and input  
VDDP  
20,21,24,25,27, programming pins (Spread#, PWR_DN#, SEL133/100#)  
28  
31  
30  
3.3 V Power Supply for 48MHz output buffer and internal PLL  
circuitry.  
VDD48  
VDD3V66  
VDDC  
39, 40  
45  
32,33,34,35,37, 3.3 V Power Supply for 3V66M buffers, digital core circuitry, and  
38,41  
44  
input programming pins (CPU_STP#, PCI_STP#, SEL(0:1)).  
Power Supply pin for CPU output buffer. Typically connected to  
2.5V  
49  
56  
50  
53,55  
Power Supply pin for CPU/2. Typically connected to 2.5V  
Power Supply pin for IOAPIC(0:1). Typically connected to 2.5V  
Common Ground pins.  
VDDC/2  
VDDI  
VSS  
1,9,14,15,29,  
22, 23, 36, 42,  
43,47, 51,54  
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins  
their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571  
WWW.IMICORP.COM  
Rev 1.0  
11/1/1999  
Page 3 of 19  
1234567...19

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