C8051F226
25 MIPS, 8 kB Flash, 8-Bit ADC, 48-Pin Mixed-Signal MCU
Analog Peripherals
High-Speed 8051 µC Core
8-Bit ADC
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Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
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±1/2 LSB INL; no missing codes
Programmable throughput up to 100 ksps
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Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler; up to 21 interrupt sources
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32 external inputs (each port I/O can be configured as an ADC input on-
the-fly)
Memory
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
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1280 bytes data RAM
Data-dependent windowed interrupt generator
8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
V
from external pin or V
TwoRcEoFmparators
DD
reserved)
Digital Peripherals
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Programmable hysteresis
Configurable to generate interrupts or reset
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32 port I/O; all are 5 V tolerant
Hardware SPI™ and UART serial ports available concurrently
3 general-purpose 16-bit counter/timers
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VDD Monitor and Brown-out Detector
On-Chip JTAG Debug
Dedicated watchdog timer; bidirectional reset
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On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
Clock Sources
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Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Fully compliant with IEEE 1149.1 specification
Supply Voltage: 2.7 to 3.6 V
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Typical operating current: 9 mA at 25 MHz
Typical stop mode current: <0.1 uA
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48-Pin TQFP
- Temperature Range: –40 to +85 °C
VDD
VDD
Analog/Digital
Power
P0.0/TX
Port 0
P
0
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
Latch
UART
P
0
GND
GND
NC
D
r
P0.5/T1
M
U
X
Timer 0
Timer 1
Timer 2
NC
P0.6/T2
NC
v
P0.7/T2EX
Port 1
Latch
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
TCK
TMS
TDI
8 kB FLASH
P
1
8
0
5
1
JTAG
Logic
P
1
Debug HW
WDT
CP0+
CP0-
CP0
TDO
CP0
CP1
256 byte
RAM
D
r
Reset
M
U
X
RST
CP1+
CP1-
v
CP1
1024 byte
XRAM
VDD
SYSCLK
MONEN
Monitor
P2.0/NSS
P2.1/MISO
P2.2/MOSI
P2.3/SCK
P2.4
C
o
r
P
2
P
2
Port 2
External
Oscillator
Circuit
XTAL1
XTAL2
SFR Bus
Latch
SPI
System Clock
D
r
M
U
X
P2.5
P2.6
e
Internal
v
P2.7
Oscillator
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P
3
Port 3
Latch
D
r
v
A
M
U
X
8-bit
AIN0-AIN31
PGA
100 ksps
ADC
VDD
VREF
General Purpose
Copyright © 2004 by Silicon Laboratories
6.15.2004