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BW0406X_LGISDN PDF预览

BW0406X_LGISDN

更新时间: 2022-01-18 22:24:00
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其他 - ETC 解码器编解码器综合业务数字网
页数 文件大小 规格书
14页 275K
描述
BW0406X_LGISDN Sigma-Delta Voice CODEC|Data Sheet

BW0406X_LGISDN 数据手册

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REV 1.1 2002/07/30  
Sigma-Delta Voice CODEC  
BW0406X_lgisdn  
FEATURES  
GENERAL DESCRIPTION  
- Single chip voice line Codec  
(A/D, D/A converter included)  
- Oversampled Sigma Delta modulator/  
Demodulator  
The BW0406X_lgisdn is Sigma-Delta CODEC for  
speech and telephony applications. The product contains  
both digital IIR/FIR filter and smoothing filter. The  
normal input and output channels have /A law format  
m
- Input/Output format : 8bit -law/A-law and  
m
with 38dB signal to distortion ratio.  
linear 14bit  
The input and output of this device is compressed  
* These three types are easily selectible by  
control pins  
form(A-law, -law) and 14bit linear which can be  
m
* When serial interface mode, the 14bit  
linear data has 16bit format with two don't  
care bits from LSB  
easily determined by control select pins  
An on-chip voltage reference circuit is included to  
allow the single supply operation  
- Sigma Delta ADC.  
* 256X Oversampling  
* On chip Decimation Filter  
* On chip Smoothing Filter  
- Sigma Delta DAC.  
TYPICAL APPLICATIONS  
Speech Processing  
-
* 256X Oversampling  
* On chip 256X Interpolation Filter  
* On chip Analog Post Filter  
- Single ended Input and Output.  
- Sampling Rate of 8~11KHz  
- On chip voltage reference circuitry  
- Single +3.3V Power Supply  
- 2Vpp In, Output signal swing  
- Power Consumption  
(Recognition, Synthesis, Compression etc.)  
Telephony  
Modem  
-
-
* Operating Mode : 10mW Typ(3.3V)  
* Powerdown Mode : 33 W Typ(3.3V)  
m
FUNCTIONAL BLOCK DIAGRAM WITH INPUT/OUPUT APPLICATION  
ALOOP MUTE TPOST TDECI  
REFH REFL  
SINPO<1:0> SDECI<1:0>  
DAPWD  
AINFB0  
SDOUT  
ADC Serial  
Output  
CIS<0>  
+
+
AINFB1  
-
-
Serial Interface  
Analog Input0  
Analog Input1  
1. 14bit Linear PCM in  
16bit format  
m
Analog  
Modulator  
Decimation  
filter  
DS  
2. -law  
3. A-law  
SDIN  
DAC Serial  
Interface  
CIS<1>  
Voltage Reference  
Output  
VREFOUT  
Voltage Reference  
APOSTOUT0  
APOSTOUT1  
DADS  
LCS  
Interpolation  
filter  
Analog Output0  
Analog Output1  
Analog  
Postfilter  
Digital  
Modulator  
DS  
COS<1:0>>  
Differential to  
Single circuit +  
Smoothing filter  
Selectible  
powerdown circuit  
CPSEL  
COS<1:0>  
CIS<1:0>  
X256FS BCK  
SYNC  
RST  
VDDD  
VSSD VDDA VSSA  
ADPWD DAPWD  
SAMSUNG ELECTRONICS Co. LTD  

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