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BU99022NUX-3

更新时间: 2024-01-12 20:54:03
品牌 Logo 应用领域
罗姆 - ROHM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
26页 585K
描述
I2C BUS 2kbit 2kbit 2ports serial EEPROM

BU99022NUX-3 数据手册

 浏览型号BU99022NUX-3的Datasheet PDF文件第1页浏览型号BU99022NUX-3的Datasheet PDF文件第2页浏览型号BU99022NUX-3的Datasheet PDF文件第4页浏览型号BU99022NUX-3的Datasheet PDF文件第5页浏览型号BU99022NUX-3的Datasheet PDF文件第6页浏览型号BU99022NUX-3的Datasheet PDF文件第7页 
Datasheet  
BU99022NUX-3  
AC operating characteristic  
(Unless otherwise specified, Ta=40+85, VCC=1.75.5V)  
Limit  
Typ.  
Parameter  
Symbol  
Unit  
Min.  
Max.  
400  
SCL frequency  
fSCL  
tHIGH  
tLOW  
tR  
kHz  
μs  
μs  
μs  
μs  
μs  
μs  
ns  
Data clock “HIGH“ time  
Data clock “LOW“ time  
SDA, SCL rise time *1*2  
SDA, SCL fall time *1*2  
Start condition hold time  
Start condition setup time  
Input data hold time  
0.6  
1.2  
1.0  
1.0  
tF  
tHD:STA  
tSU:STA  
tHD:DAT  
tSU:DAT  
tPD  
0.6  
0.6  
0
Input data setup time  
Output data delay time  
Output data hold time  
Stop condition setup time  
100  
0.1  
0.1  
0.6  
1.2  
ns  
0.9  
μs  
μs  
μs  
μs  
ms  
μs  
μs  
μs  
μs  
tDH  
tSU:STO  
tBUF  
Bus release time before  
transfer start  
Internal write cycle time  
tWR  
5
Noise removal valid period  
(SDA, SCL terminal)  
tI  
0.1  
WP hold time  
tHD:WP  
tSU:WP  
tHIGH:WP  
1.0  
0.1  
1.0  
WP setup time  
WP valid time  
*1 Not 100% TESTED.  
*2 It is recommended that tR/tF is less than 300ns fundamentally.  
When tR/tF is more than 300ns and less than 1us, it is possible that other device on the  
same bus are entered unintended start/stop condition. For prevent it, note in designing  
the AC timing.  
Condition  
Input data level:VIL=0.2×Vcc VIH=0.8×Vcc  
Input data timing refarence level: 0.3×Vcc/0.7×Vcc  
Output data timing refarence level: 0.3×Vcc/0.7×Vcc  
Rise/Fall time : 20ns  
Sync data input / output timing  
tR  
tF  
tHIGH  
70%  
70%  
30%  
SCL  
70% 70%  
70%  
30%  
30%  
30%  
tLOW  
tHD:DAT  
tSU:DAT  
DATA(n)  
DATA(1)  
70%  
70%  
70%  
70%  
70%  
30%  
ACK  
D0 ACK  
D1  
SDA  
(input)  
tWR  
tPD  
tDH  
tBUF  
30%  
30%  
70%  
30%  
70%  
30%  
SDA  
(output)  
tSU:WP  
tHD:WP  
STOP CONDITION  
Input read at the rise edge of SCL  
Data output in sync with the fall of SCL  
Fig.2 WP timing at write execution  
Fig.1-(a) Sync data input / output timing  
70%  
70%  
70%  
DATA(n)  
DATA(1)  
70%  
D1  
ACK  
ACK  
D0  
tSU:STA  
tHD:STA  
tSU:STO  
tWR  
tHIGH:WP  
70%  
30%  
30%  
70%  
70%  
STOP CONDITION  
START CONDITION  
Fig.1-(b) Start-stop bit timing  
Fig.3 WP timing at write cancel  
70%  
70%  
ACK  
D0  
write data  
(n-th address)  
tWR  
STOP CONDITION START CONDITION  
Fig.1-(c) Write cycle timing  
www.rohm.com  
© 2011 ROHM Co., Ltd. All rights reserved.  
TSZ02201-0R2R0G100010-1-2  
2011.12.19 Rev.001  
3/23  
TSZ2211114001  

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