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BU4528BF PDF预览

BU4528BF

更新时间: 2024-01-14 19:09:44
品牌 Logo 应用领域
罗姆 - ROHM 振荡器预分频器多谐振动器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
5页 65K
描述
Dual monostable multivibrator

BU4528BF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:LSOP, SOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.41其他特性:RETRIGGERABLE
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
JESD-609代码:e3/e2长度:10 mm
逻辑集成电路类型:MONOSTABLE MULTIVIBRATOR数据/时钟输入次数:2
功能数量:2端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:LSOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE
峰值回流温度(摄氏度):260电源:5/15 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:Prescaler/Multivibrators最大供电电压 (Vsup):16 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN/TIN COPPER
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:10
宽度:4.4 mmBase Number Matches:1

BU4528BF 数据手册

 浏览型号BU4528BF的Datasheet PDF文件第2页浏览型号BU4528BF的Datasheet PDF文件第3页浏览型号BU4528BF的Datasheet PDF文件第4页浏览型号BU4528BF的Datasheet PDF文件第5页 
Standard ICs  
Dual monostable multivibrator  
BU4528B / BU4528BF  
The BU4528B and BU4528BF are monostable multivibrators with trigger and reset functions that can be activated.  
Each chip has two built-in circuits.  
Triggers can initiate both rising and falling in response to Input A and Input B. As the output monostable pulse width  
is determined by the time constant of the external resistance (Rx) and the capacitor (Cx), a wide range of output  
pulse widths can be set.  
Setting the RESET input to "L" enables external asynchronous resetting and this RESET input can be utilized to  
reduce the time from the trigger disable input or the power on until the BU4528B and BU4528BF are ready for mono-  
stable operation.  
Features  
1) Low power dissipation.  
4) High fan-out.  
2) Wide range of operating power supply voltages.  
3) High input impedance.  
5) Direct drive of 2 L-TTL inputs and 1 LS-TTL input.  
Block diagram  
T11  
1
2
3
4
5
6
7
8
16 VDD  
15 T12  
T21  
RESET1  
T22  
14  
13  
A1  
B1  
RESET2  
12 A2  
11 B2  
10 Q2  
Q1  
Q1  
VSS  
9
Q2  
Truth table  
Logic circuit diagram  
INPUT  
A
OUTPUT  
RESET  
B
H
Q
Q
CX  
RX  
VDD  
H
H
H
H
H
H
L
L
T1  
T2  
A
B
Q
Q
L
Not Triggered  
Not Triggered  
Not Triggered  
Not Triggered  
H
L, H,  
L
RESET  
H
L, H,  
X
X
X
L
H
X
Not Triggered  
1

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