Datasheet > BTS7200-4EPA

BTS7200-4EPA

更新时间： 2024-02-05 22:44:31

品牌	Logo	应用领域
英飞凌 - INFINEON		驱动接口集成电路
页数	文件大小	规格书
61页	1664K
描述
The BTS7200-4EPA is a Smart High-Side Power Switch, providing protection functions and diagnosis. The device is integrated in SMART7 technology.

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BTS7200-4EPA 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.64	接口集成电路类型：	BUFFER OR INVERTER BASED PERIPHERAL DRIVER
Base Number Matches：	1

BTS7200-4EPA 数据手册

BTS7200-4EPA

PROFET™ +2 12V

General Product Characteristics

Table 5

Functional Range - Supply Voltage and Temperature¹⁾(continued)

Parameter

Symbol

Values

Unit Note or

Test Condition

Number

Min. Typ. Max.

Supply Voltage Range

reached after Overload

Protection activation

leading to“Undervoltage on

V_S” condition

V_S(EXT,CVG)

–

3.1

C_VSGNDis required

when the Overload

Protection is

triggered (see

Chapter 8.2) and

the observed

P_4.3.0.7

number of retries is

different from what

specified in

Chapter 8.3.1

Upper Extended Supply

Voltage Range for Operation

V_S(EXT,UP)

–

P_4.3.0.3

P_4.3.0.5

(parameter

deviations possible)

Junction Temperature

T_J

-40

150 °C

–

1) Not subject to production test - specified by design.

2) In case of V_Svoltage decreasing: V_{S(EXT,LOW),MIN}= 3.1 V. In case of V_Svoltage increasing: V_{S(EXT,LOW),MIN}= 4.1 V.

3) Protection functions still operative.

Note:

Within the functional or operating range, the IC operates as described in the circuit description. The

electrical characteristics are specified within the conditions given in the Electrical Characteristics

tables.

4.4

Thermal Resistance

Note:

This thermal data was generated in accordance with JEDEC JESD51 standards. For more

information, go to www.jedec.org.

Table 6

Thermal Resistance¹⁾

Parameter

Symbol

Values

Typ.

2.2

Unit Note or

Test Condition

Number

Min.

Max.

Thermal Characterization

Parameter Junction-Top

Ψ_JTOP

–

3.6

K/W

P_4.4.0.1

P_4.4.0.2

Thermal Resistance

Junction-to-Case

R_thJC

–

1.6

2.6

–

K/W

simulated at

exposed pad

Thermal Resistance

Junction-to-Ambient

R_thJA

32.8

K/W

P_4.4.0.3

1) Not subject to production test - specified by design.

2) According to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was

simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable

a thermal via array under the exposed pad contacted the first inner copper layer. Simulation done at T_A= 105°C,

_DISSIPATION= 1 W.

Data Sheet

Rev. 1.10

2020-12-14

1...7 8 91011 12 13...61

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