Very Low Power/Voltage CMOS SRAM
256K X 8 bit
BSI
BS62LV2001
FEATURES
DESCRIPTION
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
The BS62LV2001 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates in a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3V operation.
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
• High speed access time :
-70
-10
70ns(Max.) at Vcc = 3.0V
100ns(Max.) at Vcc = 3.0V
The BS62LV2001 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS62LV2001 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
• All I/O pins are 3V/5V tolerant
PRODUCT FAMILY
BLOCK DIAGRAM
PIN CONFIGURATIONS
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
OE
2
A9
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A13
A17
3
A8
4
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A15
5
Address
Memory Array
1024 x 2048
6
A16
20
1024
Row
BS62LV2001TC
BS62LV2001STC
BS62LV2001TI
BS62LV2001STI
7
A14
A12
A7
Input
8
9
Decoder
Buffer
10
11
12
13
14
15
16
A6
A5
A4
A6
A1
2048
A5
A2
A4
A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Column I/O
8
Input
Buffer
Write Driver
Sense Amp
A17
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
8
8
Data
256
Output
Buffer
Column Decoder
16
A6
A5
A9
BS62LV2001SC
BS62LV2001SI
A4
A11
OE
CE1
CE2
WE
OE
Vdd
Gnd
A3
Control
A2
Address Input Buffer
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A1
A0
DQ0
DQ1
DQ2
GND
A9 A8 A3 A2 A1 A0 A10
A11
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.5
April 2002
R0201-BS62LV2001
1