Very Low Power/Voltage CMOS SRAM
256K X 8 bit
BSI
BS62LV2003
DESCRIPTION
FEATURES
The BS62LV2003 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates from a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3.0V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
• Wide Vcc operation voltage : 2.4V ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
• High speed access time :
-70
-10
70ns(Max.) at Vcc = 3.0V
100ns(Max.) at Vcc = 3.0V
The BS62LV2003 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2003 is available in the JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
and 8mmx20mm TSOP.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
PRODUCT
FAMILY
OPERATING
Vcc
STANDBY
Operating
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
TEMPERATURE
RANGE
Vcc= 3.0V
Vcc=3.0V
Vcc=3.0V
BS62LV2003TC
BS62LV2003STC
BS62LV2003SC
BS62LV2003TI
BS62LV2003STI
BS62LV2003SI
TSOP-32
STSOP-32
SOP-32
TSOP-32
STSOP-32
SOP-32
+0 O C to +70 O
-40 O C to +85 O
C
C
2.4V ~ 3.6V
2.4V ~3.6V
70 / 100
0.7uA
20mA
70 / 100
1.5uA
25mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
OE
2
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
3
A8
A13
A17
4
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
5
A15
6
Address
Memory Array
1024 x 2048
A16
20
BS62LV2003TC
BS62LV2003STC
BS62LV2003TI
BS62LV2003STI
7
1024
Row
A14
A12
A7
8
Input
9
Decoder
10
11
12
13
14
15
16
Buffer
A6
A5
A4
A6
A1
A5
A2
2048
A4
A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Column I/O
8
Input
Buffer
Write Driver
Sense Amp
A17
A16
A14
A12
A7
1
VCC
A15
CE2
WE
A13
A8
32
8
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
8
Data
3
256
Output
Buffer
4
5
Column Decoder
16
A6
6
A5
7
A9
BS62LV2003SC
BS62LV2003SI
A4
8
A11
OE
CE1
CE2
WE
OE
Vdd
Gnd
A3
9
Control
Address Input Buffer
A2
10
11
12
13
14
15
16
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
A1
A0
DQ0
DQ1
DQ2
GND
A9 A8 A3 A2 A1 A0 A10
A11
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.4
April 2002
R0201-BS62LV2003
1