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BS616LV8011AI PDF预览

BS616LV8011AI

更新时间: 2024-01-04 12:49:40
品牌 Logo 应用领域
BSI 静态存储器
页数 文件大小 规格书
9页 193K
描述
Very Low Power/Voltage CMOS SRAM 512K X 16 bit

BS616LV8011AI 数据手册

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Very Low Power/Voltage CMOS SRAM  
512K X 16 bit  
BSI  
BS616LV8011  
„ DESCRIPTION  
„ FEATURES  
The BS616LV8011 is a high performance, very low power CMOS Static  
Random Access Memory organized as 524,288 words by 16 bits and  
operates from a wide range of 2.7V to 3.6V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current  
of 1uA and maximum access time of 70/100ns in 3V operation.  
Easy memory expansion is provided by an active LOW chip  
enable(CE1,CE2) and active LOW output enable(OE) and three-state  
output drivers.  
• Very low operation voltage : 2.7 ~ 3.6V  
• Very low power consumption :  
Vcc = 3.0V C-grade: 40mA (Max.) operating current  
I-grade : 50mA (Max.) operating current  
1uA (Typ.) CMOS standby current  
• High speed access time :  
-70  
-10  
70ns (Max.) at Vcc=3.0V  
100ns (Max.) at Vcc=3.0V  
• Automatic power down when chip is deselected  
• Three state outputs and TTL compatible  
• Fully static operation  
The BS616LV8011 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
The BS616LV8011 is available in 48-pin BGA package.  
• Data retention supply voltage as low as 1.5V  
• Easy expansion with CE1,CE2 and OE options  
„ PRODUCT FAMILY  
POWER DISSIPATION  
SPEED  
(ns)  
STANDBY  
Operating  
OPERATING  
PRODUCT FAMILY  
Vcc  
(ICCSB1, Max)  
(ICC, Max)  
PKG TYPE  
TEMPERATURE  
RANGE  
Vcc=3.0V  
70 / 100  
70 / 100  
Vcc=3.0V  
16uA  
Vcc=3.0V  
40mA  
50mA  
BS616LV8011AC  
BS616LV8011AI  
+0 O C to +70O  
-40O C to +85O  
C
C
2.7V ~ 3.6V  
2.7V ~ 3.6V  
BGA-48-0608  
BGA-48-0608  
24uA  
„ PIN CONFIGURATIONS  
„ BLOCK DIAGRAM  
A4  
A3  
A2  
A1  
A0  
1
X
2
3
4
5
6
Address  
Input  
A0  
A1  
A2  
CE2  
A
B
C
D
E
F
OE  
22  
2048  
A17  
A16  
A15  
A14  
A13  
A12  
Row  
Memory Array  
2048 x 4096  
Buffer  
D8  
A3  
A4  
X
CE1  
D0  
D2  
Decoder  
D9  
D10  
A5  
A6  
A7  
D1  
D3  
4096  
Data  
16  
16  
Column I/O  
Input  
D0  
D11  
D12  
D13  
A17  
Buffer  
VSS  
VCC  
D14  
VCC  
.
.
.
.
.
.
.
.
Write Driver  
Sense Amp  
16  
256  
Vss  
A14  
A12  
A9  
A16  
A15  
A13  
A10  
D4  
D5  
Data  
VSS  
D6  
16  
Output  
Buffer  
Column Decoder  
D15  
16  
CE1  
CE2  
D15 NC.  
A8  
G
H
Control  
Address Input Buffer  
WE  
D7  
OE  
WE  
A11 A10 A9 A8 A7  
A6 A5 A18  
A18  
A11  
NC.  
Vcc  
Gnd  
48-Ball CSP top View  
X: Don’t care  
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.  
Revision 2.3  
April 2002  
R0201-BS616LV8011  
1

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