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BS616LV8012

更新时间: 2024-02-07 21:08:09
品牌 Logo 应用领域
BSI 静态存储器
页数 文件大小 规格书
9页 208K
描述
Very Low Power/Voltage CMOS SRAM 512K X 16 bit

BS616LV8012 数据手册

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Very Low Power/Voltage CMOS SRAM  
512K X 16 bit  
BSI  
BS616LV8012  
„ FEATURES  
„ DESCRIPTION  
• Very low operation voltage : 2.4~5.5V  
• Very low power consumption :  
The BS616LV8012 is a high performance, very low power CMOS Static  
Random Access Memory organized as 524,288 words by 16 bits and  
operates from a wide range of 2.4V to 5.5V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current  
of 0.5uA and maximum access time of 70/100ns in 3V operation.  
Easy memory expansion is provided by an active LOW chip enable(CE1),  
active HIGH chip enable (CE2), active LOW output enable(OE) and  
three-state output drivers.  
Vcc = 3.0V C-grade: 20mA (Max.) operating current  
I-grade : 25mA (Max.) operating current  
0.5uA (Typ.) CMOS standby current  
Vcc = 5.0V C-grade: 45mA (Max.) operating current  
I-grade : 50mA (Max.) operating current  
3uA (Typ.) CMOS standby current  
• High speed access time :  
-70  
-10  
70ns (Max.) at Vcc=3V  
100ns (Max.) at Vcc=3V  
The BS616LV8012 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
• Automatic power down when chip is deselected  
• Three state outputs and TTL compatible  
• Fully static operation  
The BS616LV8012 is available in 48-pin BGA package.  
• Data retention supply voltage as low as 1.5V  
• Easy expansion with CE2,CE1 and OE options  
• I/O Configuration x8/x16 selectable by LB and UB pin  
„ PRODUCT FAMILY  
POWER DISSIPATION  
SPEED  
(ns)  
STANDBY  
Operating  
OPERATING  
Vcc  
(ICCSB1, Max)  
(ICC, Max)  
PRODUCT FAMILY  
PKG TYPE  
TEMPERATURE  
RANGE  
Vcc=3V  
70 / 100  
70 / 100  
Vcc=3V  
Vcc=5V  
30uA  
Vcc=3V  
Vcc=5V  
45mA  
50mA  
BS616LV8012BC  
BS616LV8012BI  
+0 O C to +70O  
-40O C to +85O  
C
C
2.4V ~ 5.5V  
2.4V ~ 5.5V  
3uA  
6uA  
20mA  
25mA  
BGA-48-0810  
BGA-48-0810  
100uA  
„ PIN CONFIGURATIONS  
„ BLOCK DIAGRAM  
A4  
A3  
A2  
1
2
3
4
5
6
A1  
A0  
A17  
A16  
A15  
A14  
A13  
A12  
Address  
Input  
A
B
C
D
LB  
OE  
A0  
A1  
A2  
CE2  
22  
2048  
Row  
Decoder  
Memory Array  
2048 x 4096  
Buffer  
D8  
D9  
UB  
A3  
A5  
A4  
A6  
CE1  
D1  
D0  
D2  
D10  
4096  
Data  
16  
16  
Column I/O  
Input  
D0  
VSS D11  
VCC D12  
A17  
A7  
D3  
D4  
VCC  
Buffer  
.
.
.
.
.
.
.
.
Write Driver  
Sense Amp  
16  
256  
A16  
A15  
A13  
A10  
Data  
VSS  
A14  
VSS  
D6  
E
F
16  
Output  
Buffer  
Column Decoder  
D15  
D5  
D14  
D15  
A18  
D13  
CE2  
16  
CE1  
WE  
OE  
WE  
A11  
D7  
A12  
A9  
G
H
N.C  
A8  
Control  
Address Input Buffer  
UB  
LB  
A11 A10 A9 A8 A7  
A6 A5 A18  
NC  
Vcc  
Vss  
48-Ball CSP top View  
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.  
Revision 2.4  
April 2002  
R0201-BS616LV8012  
1

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