Very Low Power CMOS SRAM
128K X 16 bit
BS616LV2019
Pb-Free and Green package materials are compliant to RoHS
FEATURES
DESCRIPTION
y Wide VCC operation voltage : 2.4V ~ 3.6V
y Very low power consumption :
The BS616LV2019 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 by 16 bits and
operates form a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with maximum CMOS standby
current of 3/5uA at 3V at 70/85OC and maximum access time of
55/70ns.
VCC = 3.0V
Operation current : 25mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 3/5uA (Max.) at 70/85OC
y High speed access time :
-55
-70
55ns(Max.) at VCC=2.7~3.6V
70ns(Max.) at VCC=2.4~3.6V
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
The BS616LV2019 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616LV2019 is available in DICE form, JEDEC standard
48-pin TSOP Type I package and 48-ball BGA package.
y Automatic power down when chip is deselected
y Easy expansion with CE and OE options
y I/O Configuration x8/x16 selectable by LB and UB pin.
y Three state outputs and TTL compatible
y Fully static operation
y Data retention supply voltage as low as 1.5V
POWER CONSUMPTION
POWER DISSIPATION
Operating
STANDBY
PRODUCT
FAMILY
OPERATING
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
TEMPERATURE
VCC=3.0V
VCC=3.0V
1MHz
10MHz
9mA
fMax.
BS616LV2019DC
BS616LV2019AC
BS616LV2019TC
BS616LV2019AI
BS616LV2019TI
DICE
Commercial
3.0uA
1.5mA
23mA
BGA-48-0608
TSOP I-48
BGA-48-0608
TSOP I-48
+0OC to +70OC
Industrial
5.0uA
2mA
10mA
25mA
-40OC to +85OC
PIN CONFIGURATIONS
BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
2
NC
A6
A7
A8
A9
A10
A11
A15
A14
A13
A12
3
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
4
5
6
Address
Input
1024
Memory Array
1024 x 2048
10
7
A8
8
Row
Decoder
NC
NC
WE
CE2
NC
UB
LB
9
Buffer
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
BS616LV2019TC
BS616LV2019TI
2048
NC
NC
A7
DQ0
.
.
.
.
.
.
Data
16
Column I/O
16
Input
.
.
.
.
.
.
A6
Buffer
A5
Write Driver
Sense Amp
A4
A3
GND
CE
16
16
A2
Data
Output
Buffer
128
A1
A0
Column Decoder
DQ15
1
2
3
4
5
6
7
CE2,CE
WE
NC
A
B
C
D
E
F
LB
OE
A0
A1
A2
Address Input Buffer
OE
UB
LB
Control
D8
D9
UB
D10
D11
D12
D13
NC
A3
A5
A4
A6
CE
D1
D0
D2
A16 A0 A1 A2 A3
A5
A4
VCC
VSS
VSS
VCC
D14
D15
NC
NC
NC
A14
A12
A9
A7
D3
VCC
VSS
D6
A16
A15
A13
A10
D4
D5
G
H
WE
A11
D7
A8
NC
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS616LV2019
Revision
Oct.
1.4
1
2008