Very Low Power CMOS SRAM
128K X 16 bit
BS616LV2019
Pb-Free and Green package materials are compliant to RoHS
n FEATURES
n DESCRIPTION
ŸWide VCC operation voltage : 2.4V ~ 3.6V
ŸVery low power consumption :
The BS616LV2019 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 by 16 bits and
operates form a wide range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical CMOS standby
current of 0.3uA at 3.0V/25OC and maximum access time of 55ns at
2.7V/85OC.
VCC = 3.0V
Operation current : 25mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.3uA (Typ.) at 25OC
ŸHigh speed access time :
-55
-70
55ns(Max.) at VCC=2.7~3.6V
70ns(Max.) at VCC=2.4~3.6V
Easy memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state output
drivers.
ŸAutomatic power down when chip is deselected
ŸEasy expansion with CE and OE options
ŸI/O Configuration x8/x16 selectable by LB and UB pin.
ŸThree state outputs and TTL compatible
ŸFully static operation
The BS616LV2019 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS616LV2019 is available in DICE form, JEDEC standard
48-pin TSOP Type I package and 48-ball BGA package.
ŸData retention supply voltage as low as 1.5V
n POWER CONSUMPTION
POWER DISSIPATION
Operating
STANDBY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
VCC=3.0V
VCC=3.0V
1MHz
10MHz
9mA
fMax.
BS616LV2019DC
BS616LV2019AC
BS616LV2019TC
BS616LV2019AI
BS616LV2019TI
DICE
Commercial
3.0uA
1.5mA
23mA
BGA-48-0608
TSOP I-48
BGA-48-0608
TSOP I-48
+0OC to +70OC
Industrial
5.0uA
2mA
10mA
25mA
-40OC to +85OC
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
A6
A7
A8
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
A9
A10
A11
A15
A14
A13
A12
Address
Input
1024
Memory Array
1024 x 2048
10
A8
Row
NC
NC
WE
CE2
NC
UB
LB
NC
NC
A7
A6
A5
A4
A3
A2
A1
9
Decoder
Buffer
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
BS616LV2019TC
BS616LV2019TI
2048
DQ0
Data
Input
Buffer
16
16
Column I/O
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
.
GND
CE
A0
16
.
16
Data
Output
Buffer
.
.
128
Column Decoder
DQ15
1
2
3
4
5
6
7
CE2,CE
WE
A
B
C
D
E
F
LB
OE
A0
A1
A2
NC
Address Input Buffer
OE
Control
D8
D9
UB
D10
D11
D12
D13
NC
A3
A5
A4
A6
CE
D1
D0
D2
UB
LB
A16 A0 A1 A2 A3 A4 A5
VCC
VSS
VSS
VCC
D14
D15
NC
NC
NC
A14
A12
A9
A7
D3
VCC
VSS
D6
A16
A15
A13
A10
D4
D5
G
H
WE
A11
D7
A8
NC
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS616LV2019
Revision 1.3
May. 2006
1