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BS616LV2018AC PDF预览

BS616LV2018AC

更新时间: 2024-01-10 09:46:40
品牌 Logo 应用领域
BSI 静态存储器
页数 文件大小 规格书
11页 221K
描述
Very Low Power/Voltage CMOS SRAM 128K X 16 bit

BS616LV2018AC 数据手册

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Very Low Power/Voltage CMOS SRAM  
128K X 16 bit  
BSI  
BS616LV2018  
„ FEATURES  
„ DESCRIPTION  
• Very low operation voltage : 2.4 ~ 3.6V  
• Very low power consumption :  
The BS616LV2018 is a high performance, very low power CMOS Static  
Random Access Memory organized as 131,072 words by 16 bits and  
operates from a wide range of 2.4V to 3.6V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current  
of 0.1uA and maximum access time of 70ns in 3V operation.  
Easy memory expansion is provided by active LOW chip  
enable(CE), active LOW output enable(OE) and three-state output  
drivers.  
Vcc = 3.0V  
C-grade: 16mA (Max.) operating current  
I -grade: 20mA (Max.) operating current  
0.1uA (Typ.) CMOS standby current  
• High speed access time :  
-70  
70ns (Max.) at Vcc = 3.0V  
• Automatic power down when chip is deselected  
• Three state outputs and TTL compatible  
• Fully static operation  
The BS616LV2018 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
The BS616LV2018 is available in DICE form, JEDEC standard 48-pin  
TSOP Type I package and 48-ball BGA package.  
• Data retention supply voltage as low as 1.5V  
• Easy expansion with CE and OE options  
• I/O Configuration x8/x16 selectable by LB and UB pin  
„ PRODUCT FAMILY  
POWER DISSIPATION  
SPEED  
(ns)  
STANDBY  
Operating  
PRODUCT  
FAMILY  
OPERATING  
Vcc  
PKG TYPE  
(I  
, Max)  
(I , Max)  
CC  
CCSB1  
TEMPERATURE  
RANGE  
Vcc=  
Vcc=3.0V  
Vcc=3.0V  
3.0V  
BS616LV2018DC  
BS616LV2018TC  
BS616LV2018AC  
DICE  
0 O C to +70 O  
C
70  
70  
0.7 uA  
TSOP1-48  
16 mA  
BGA-48-0608  
2.4V ~3.6V  
BS616LV2018DI  
DICE  
-40 O C to +85 O  
C
1.5 uA  
20 mA  
BS616LV2018TI  
BS616LV2018AI  
TSOP1-48  
BGA-48-0608  
„ BLOCK DIAGRAM  
„ PIN CONFIGURATIONS  
A8  
A13  
A15  
1
2
3
4
5
6
Address  
20  
A16  
1024  
A14  
A
B
C
D
E
F
LB  
D8  
D9  
OE  
UB  
A0  
A3  
A1  
A4  
A2  
N.C.  
D0  
Input  
Row  
Memory Array  
1024 x 2048  
A12  
A7  
A6  
A5  
A4  
Buffer  
Decoder  
CE  
D1  
D10  
D11  
D12  
D13  
A5  
A6  
D2  
2048  
Data  
VSS  
VCC  
N.C.  
N.C.  
A14  
A12  
A9  
A7  
D3  
VCC  
VSS  
16  
16  
16  
Column I/O  
Input  
DQ0  
Buffer  
.
.
.
.
.
.
.
.
Write Driver  
Sense Amp  
A16  
A15  
A13  
A10  
D4  
128  
Data  
D14  
D15  
N.C.  
D5  
D6  
16  
Output  
Buffer  
Column Decoder  
DQ15  
G
H
WE  
A11  
D7  
N.C.  
A8  
14  
CE  
WE  
OE  
UB  
N.C.  
Control  
Address Input Buffer  
LB  
A11 A9 A3 A2 A1  
48-ball BGA top view  
A0 A10  
Vcc  
Gnd  
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.  
Revision 2.0  
April 2002  
R0201-BS616LV2018  
1

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