BQ2204ASN-NG4 PDF预览

BQ2204ASN-NG4

更新时间: 2025-07-20 12:33:03
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德州仪器 - TI 静态存储器控制器
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描述
X4 SRAM Nonvolatile Controller Unit

BQ2204ASN-NG4 数据手册

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bq2204A  
X4 SRAM Nonvolatile Controller Unit  
During a power failure, the external  
General Description  
Features  
SRAMs are switched from the V  
CC  
supply to one of two 3V backup sup-  
plies. On a subsequent power-up, the  
SRAMs are write-protected until a  
power-valid condition exists.  
The CMOS bq2204A SRAM Non-  
volatile Controller Unit provides all  
necessary functions for converting  
up to four banks of standard CMOS  
SRAM into nonvolatile read/write  
memory.  
Power monitoring and switching  
for 3-volt battery-backup applica-  
tions  
Du r in g power-va lid oper a t ion , a  
two-input decoder transparently se-  
lect s on e of u p t o fou r ba n ks of  
SRAM.  
Write-protect control  
2-input decoder for control of up  
to 4 banks of SRAM  
A precision comparator monitors the 5V  
V
CC  
input for an out-of-tolerance condi-  
3-volt primary cell inputs  
tion. When out-of-tolerance is detected,  
the four conditioned chip-enable outputs  
are forced inactive to write-protect up to  
four banks of SRAM.  
L e s s t h a n 1 0 n s ch ip -e n a b le  
propagation delay  
5% or 10% supply operation  
Pin Connections  
Pin Names  
VOUT  
BC1–BC2  
THS  
Supply output  
3 volt primary backup cell inputs  
Threshold select input  
V
1
2
3
4
5
6
16  
15  
14  
13  
12  
11  
V
CC  
OUT  
BC  
2
BC  
CE  
CE  
CE  
CE  
1
CE  
chip-enable active low input  
Conditioned chip-enable outputs  
NC  
A
CECON1  
CECON4  
CON1  
CON2  
CON3  
CON4  
B
A–B  
NC  
Decoder inputs  
No connect  
NC  
THS  
7
8
10  
9
CE  
NC  
VCC  
VSS  
+5 volt supply input  
Ground  
V
SS  
16-Pin Narrow DIP or SOIC  
PN220401.eps  
Functional Description  
Up to four banks of CMOS static RAM can be battery-  
backed using the V and conditioned chip-enable out-  
If THS is tied to V , power-fail detection occurs at  
CC  
4.37V typical for 10% supply operation. The THS pin  
OUT  
put pins from the bq2204A. As V  
slews down during  
must be tied to V or V for proper operation.  
CC  
SS CC  
a power failure, the conditioned chip-enable outputs  
CE through CE are forced inactive independ-  
ent of the chip-enable input CE.  
If a memory access is in process to any of the four external  
banks of SRAM during power-fail detection, that memory  
cycle continues to completion before the memory is write-  
protected. If the memory cycle is not terminated within  
CON1  
CON4  
This activity unconditionally write-protects the external  
SRAM as V  
falls below an out-of-tolerance threshold  
time t  
, all four chip-enable outputs are unconditionally  
CC  
WPT  
V
PFD  
. V  
is selected by the threshold select input pin, driven high, write-protecting the controlled SRAMs.  
PFD  
THS. If THS is tied to V , the power-fail detection occurs  
SS  
at 4.62V typical for 5% supply operation.  
Dec. 1992 B  
1

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