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Features
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Core
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ARM® Cortex™-A5 Processor with ARM v7-A Thumb2® Instruction Set
CPU Frequency up to 536 MHz
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32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture (VMSA)
Fully Integrated MMU and Floating Point Unit (VFPv4)
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Memories
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One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader: Boot on
NAND Flash, SDCard, eMMC, serial DataFlash®, selectable Order
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One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed
High Bandwidth 32-bit Multi-port Dynamic Ram Controller supporting 512 Mbyte 8 bank
DDR2/LPDDR/LPDDR2
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Independent Static Memory Controller with SLC/MLC NAND Support with up to 24-bit Error Correcting Code
(PMECC)
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System running up to 166 MHz
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Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and
Real Time Clock
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Boot Mode Select Option, Remap Command
Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillators
Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed
39 DMA Channels including two 8-channel 64-bit Central DMA Controllers
64-bit Advanced Interrupt Controller
Three Programmable External Clock Signals
Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer
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Low Power Management
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Shut Down Controller
Battery Backup Registers
Clock Generator and Power Management Controller
Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
Peripherals
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LCD TFT Controller with Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion
ITU-R BT. 601/656 Image Sensor Interface
Three HS/FS/LS USB Ports with On-Chip Transceivers
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One Device Controller
One Host Controller with Integrated Root Hub (3 Downstream Ports)
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One 10/100/1000 Mbps Gigabit Ethernet Mac Controller (GMAC) with IEEE1588 support
One 10/100 Mbps Ethernet Mac Controller (EMAC)
Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN 2.0 Part A and 2.0 Part B
Softmodem Interface
Three High Speed Memory Card Hosts (eMMC 4.3 and SD 2.0)
Two Master/Slave Serial Peripheral Interface
Two Synchronous Serial Controllers
Three Two-wire Interface up to 400 Kbits supporting I2C Protocol and SMBUS
Four USARTs, two UARTs, one DBGU
Two Three-channel 32-bit Timer/Counters
SAMA5D3 Series [SUMMARY DATASHEET]
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11121AS–ATARM–31-Jan-13