Datasheet > BD616LV4017ACP70

BD616LV4017ACP70

更新时间： 2022-12-20 01:52:28

品牌	Logo	应用领域
BSI		静态存储器
页数	文件大小	规格书
10页	267K
描述
Very Low Power/Voltage CMOS SRAM 256K X 16 bit

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BD616LV4017ACP70 数据手册

浏览型号BD616LV4017ACP70的Datasheet PDF文件第10页

BSI

BS616LV4017

AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85^oC )

WRITE CYCLE

JEDEC

PARAMETER

NAME

CYCLE TIME : 70ns

(Vcc = 2.7~5.5V)

CYCLE TIME : 55ns

PARAMETER

(Vcc = 3.0~5.5V)

DESCRIPTION

Write Cycle Time

UNIT

NAME

MIN. TYP. MAX.

t_AVAX

t_E1LWH

t_AVWL

t_AVWH

t_WLWH

t_WHAX

t_BW

t_WC

t_CW

t_AS

Chip Select to End of Write

Address Setup Time

Address Valid to End of Write

Write Pulse Width

t_AW

t_WP

t_WR

Write recovery Time

(CE,WE)

(1)

Date Byte Control to End of Write

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

(LB,UB)

t_BW

t_WHZ

t_DW

t_DH

t_WLQZ

t_DVWH

t_WHDX

t_GHQZ

t_OHZ

t_WHOX

t_OW

End of Write to Output Active

NOTE :

1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1 ⁽¹⁾

ADDRESS

(3)

(10)

(5)

LB,UB

(3)

(2)

(4,11)

OHZ

D _OUT

D _IN

Revision 2.1

Jan. 2004

R0201-BS616LV4017

1...4 5 678 9 10

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