Datasheet > BD616LV4017ACP70

BD616LV4017ACP70

更新时间： 2024-01-05 08:28:02

品牌	Logo	应用领域
BSI		静态存储器
页数	文件大小	规格书
10页	267K
描述
Very Low Power/Voltage CMOS SRAM 256K X 16 bit

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BD616LV4017ACP70 数据手册

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BSI

BS616LV4017

(1,6)

WRITE CYCLE2

ADDRESS

(10)

(5)

LB,UB

(3)

(2)

(4,11)

(7)

(8)

WHZ

D _OUT

(8,9)

D _IN

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.

The data input setup and hold timing should be referenced to the second transition edge of

the signal that terminates the write.

3. T^WRis measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V^IL).

7. D^OUTis the same phase of write data of this write cycle.

8. D^OUTis the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. TCW is measured from the later of CE going low to the end of write.

11. The parameter is guaranteed but not 100% tested.

Revision 2.1

R0201-BS616LV4017

Jan.

2004

1...5 6 789 10

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