Very Low Power/Voltage CMOS SRAM
BSI 256K X 16 bit
BS616LV4017
FEATURES
• Wide Vcc operation voltage : 2.4~5.5V
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• Very low power consumption :
• I/O Configuration x8/x16 selectable by LB and UB pin
Vcc = 3.0V C-grade: 26mA (@55ns) operating current
I-grade: 27mA (@55ns) operating current
C-grade: 21mA (@70ns) operating current
I-grade: 22mA (@70ns) operating current
0.45uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 63mA (@55ns) operating current
I-grade: 65mA (@55ns) operating current
C-grade: 53mA (@70ns) operating current
I-grade: 55mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
DESCRIPTION
The BS616LV4017 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.45uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
The BS616LV4017 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• High speed access time :
-55
-70
55ns
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616LV4017 is available in DICE form, JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(
ns )
Operating
STANDBY
OPERATING
PRODUCT FAMILY
Vcc
RANGE
( ICCSB1 , Max )
( I CC , Max )
PKG TYPE
TEMPERATURE
55ns :3.0~5.5V
70ns :2.7~5.5V
Vcc =
3.0V
70ns
Vcc =
5.0V
70ns
Vcc=
Vcc=5.0V
3.0V
BS616LV4017DC
BS616LV4017EC
DICE
+0O C to +70O
C
TSOP2-44
BGA-48-0608
DICE
2.4V ~ 5.5V
55 /70
55 /70
5uA
21mA
22mA
53mA
55mA
30uA
60uA
BS616LV4017AC
BS616LV4017DI
-40O C to +85OC 2.4V ~ 5.5V
TSOP2-44
BGA-48-0608
BS616LV4017EI
BS616LV4017AI
10uA
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A5
A6
A7
OE
UB
LB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A2
A1
A0
CE
A4
A3
A2
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A17
A16
A15
A14
A13
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12
A1
Address
22
2048
A0
A17
A16
BS616LV4017EC
BS616LV4017EI
Input
Row
Memory Array
2048 x 2048
Buffer
A15
A14
A13
A12
Decoder
2048
Data
Input
Buffer
16
16
16
Column I/O
DQ0
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
128
Data
Output
16
Buffer
Column Decoder
DQ15
14
CE
WE
OE
UB
Control
Address Input Buffer
LB
A11 A10 A9 A8 A7
A6 A5
Vcc
Gnd
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 2.1
R0201-BS616LV4017
1
Jan.
2004