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BD50GA3WEFJ PDF预览

BD50GA3WEFJ

更新时间: 2024-01-11 15:01:59
品牌 Logo 应用领域
罗姆 - ROHM 开关过电流保护电源电路电容器陶瓷电容器线性稳压器IC
页数 文件大小 规格书
12页 381K
描述
BDxxGA3WEFJ系列是可提供0.3A输出电流的稳压器。输出精度为±1%。有可使用外接电阻在1.5V~13.0V范围内任意设置输出电压的可变型以及1.5V/1.8V/2.5V/3.0V/3.3V/5V/6V/7V/8V/9V/10V/12V固定输出型两种。封装组件采用散热性优良的HTSOP-J8。可用于数字家电等广泛用途。本机型内置用于防止因输出短路等发生IC破坏的过电流保护电路、关断时使电路电流为0µA的ON/OFF开关、以及防止因过负荷状态等使IC发生热破坏的温度保护电路。另外,采用了陶瓷电容器,有助于整机的小型化和长寿化。

BD50GA3WEFJ 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HVSON, SOLCC8,.12,20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:10 weeks风险等级:2.23
可调性:ADJUSTABLE标称回动电压 1:0.6 V
JESD-30 代码:R-PDSO-N8长度:3 mm
最大电网调整率 (%/V):0.086最大负载调整率 (%):1.5%
功能数量:1输出次数:1
端子数量:8工作温度TJ-Max:150 °C
最高工作温度:85 °C最低工作温度:-25 °C
最大输出电流 1:0.3 A最大输出电压 1:13 V
最小输出电压 1:1.5 V封装主体材料:PLASTIC/EPOXY
封装代码:HVSON封装等效代码:SOLCC8,.12,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法:TAPE AND REEL认证状态:Not Qualified
调节器类型:ADJUSTABLE POSITIVE SINGLE OUTPUT LDO REGULATOR座面最大高度:0.6 mm
子类别:Other Regulators表面贴装:YES
技术:CMOS端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
宽度:2 mmBase Number Matches:1

BD50GA3WEFJ 数据手册

 浏览型号BD50GA3WEFJ的Datasheet PDF文件第3页浏览型号BD50GA3WEFJ的Datasheet PDF文件第4页浏览型号BD50GA3WEFJ的Datasheet PDF文件第5页浏览型号BD50GA3WEFJ的Datasheet PDF文件第7页浏览型号BD50GA3WEFJ的Datasheet PDF文件第8页浏览型号BD50GA3WEFJ的Datasheet PDF文件第9页 
Technical Note  
BD00GA3WEFJ  
Heat Loss  
Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed  
temperature limits, and thermal design should allow sufficient margin from the limits.  
1. Ambient temperature Ta can be no higher than 85.  
2. Chip junction temperature (Tj) can be no higher than 150.  
Chip junction temperature can be determined as follows:  
Calculation based on ambient temperature (Ta)  
Tj=Ta+θj-a×W  
Reference values>  
1-layer substrate (copper foil density 0mm×0mm)  
2-layer substrate (copper foil density 15mm×15mm)  
2-layer substrate (copper foil density 70mm×70mm)  
4-layer substrate (copper foil density 70mm×70mm)  
θj-a: HTSOP-J8 153.2/W  
113.6/W  
59.2/W  
33.3/W  
Substrate size: 70×70×1.6mm3 (substrate with thermal via)  
Most of the heat loss that occurs in the BD00GA3WEFJ is generated from the output Pch FET. Power loss is determined by  
the total Vcc-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current  
conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat  
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the  
BD00GA3WEFJ make certain to factor conditions such as substrate size into the thermal design.  
Power consumption (W) = Input voltage (VCC)- Output voltage (Vo) ×Io(Ave)  
Example) Where VCC=5.0V, VO=3.3V, Io(Ave) = 0.1A,  
Power consumption (W)  
=
5.0(V)-3.3(V) ×0.1(A)  
=0.17(W)  
About equivalent series resistance ESR (ceramic capacitor etc.)  
Capacitor usually has ESREquivalent Series Resistance, and  
operates stable in ESR-OUT range, showed right. Generally, ESR of  
ceramic, tantalum and electronic capacitor etc. is different for each,  
so please be sure to check a capacitor which is going to use, and use  
it inside the stable range, showed right. Then, please evaluate for the  
actual application.  
Capacity-Bias characteristics  
100  
10  
1
0.1  
0.01  
0
50  
100  
150  
200  
IOUT [mA]  
(Characteristics example)  
www.rohm.com  
2010.04 - Rev.A  
6/11  
© 2010 ROHM Co., Ltd. All rights reserved.  

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