Datasheet > BD48E24G-TR

BD48E24G-TR

更新时间： 2022-12-29 18:40:44

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Standard CMOS Voltage Detector IC

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Datasheet

BD48xxx series BD49xxx series

●Application Information

Explanation of Operation

For both the open drain type (Fig.12) and the CMOS output type (Fig.13), the detection and release voltages are used as

threshold voltages. When the voltage applied to the V_DDpins reaches the appropriate threshold voltage, the V_OUTterminal

voltage switches from either “High” to “Low” or from “Low” to “High”. Please refer to the Timing Waveform and Electrical

Characteristics for information on hysteresis.

Because the BD48xxx series uses an open drain output type, it is necessary to connect a pull-up resistor to V_DDor another

power supply if needed [The output “High” voltage (V_OUT) in this case becomes V_DDor the voltage of the other power

supply].

Vref

OUT

GND

Fig.12 (BD48xxx series Internal Block Diagram)

Fig.13 (BD49xxx series Internal Block Diagram)

Reference Data

Examples of Leading (t_PLH) and Falling (t_PHL) Output

Part Number

BD48x45

t_PLH(µs)

39.5

t_PHL(µs)

87.8

BD49x45

32.4

52.4

V_DD=4.3V‰5.1V

V_DD=5.1V‰4.3V

*These data are for reference only.

The figures will vary with the application, so please check actual operating conditions before use.

Timing Waveform

Example: the following shows the relationship between the input voltages V_DDand the output voltage V_OUTwhen the

input power supply voltage V_DDswept up and down (the circuits are those in Fig.12 and 13).

When the power supply is turned on, the output is unstable

VDD

from after over the operating limit voltage (VOPL) until tPHL.

Therefore it is possible that the reset signal is not outputted when

the rise time of V_DDis faster than tPHL.

VDET+ΔVDET

⑤

VDET

When V_DDis greater than V_OPLbut less than the reset release

VOPL

voltage (V_DET+ ∆V_DET), the output voltages will switch to Low.

If V_DDexceeds the reset release voltage (V_DET+ ∆V_DET), then

VOUT

V_OUTswitches from L to H.

VOH

VOL

If V_DDdrops below the detection voltage (V_DET) when the power

tPLH

tPHL

tPLH

tPHL

supply is powered down or when there is a power supply

fluctuation, V_OUTswitches to L (with a delay of t_PHL).

The potential difference between the detection voltage and the

①

②

③

④

release voltage is known as the hysteresis width (∆V_DET). The

system is designed such that the output does not toggle with

power supply fluctuations within this hysteresis width, preventing

malfunctions due to noise.

Fig.14 Timing Waveform

www.rohm.com

TSZ02201-0R7R0G300030-1-2

12/15

TSZ22111・15・001

22.May.2013.Rev.008

1...9 10 111213 14 15...18

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