Technical Note
BD4156MUV
●BLOCK DIAGRAM
3.3V/1.30A
V3
V3_IN
2
4
5
3
VD
3.3V
V3
V3_IN
TSD,CL,UVLO
VD
3.3V AUX/275mA
V3AUX
V3AUX_IN
17
15
3.3V
TSD,CL,UVLO_AUX
V15_IN
V15_IN
V15
V15
1.5V/625mA
12
14
11
13
V3AUX_IN
1.5V
V3AUX_IN
VD
CPPE#
CPUSB#
SYSR
10
9
Input
logic
RCLKEN
18
Power
good
TSD,CL,UVLO
1
PERST#
EN,SYSR,CPUSB#,CPPE#
8
6
TSD
Thermal
protection
V3AUX_IN
PERST_IN#
V3_IN,V3AUX_IN,V15_IN
V3,V3AUX,V15
CL
EN
Reference
Block
V3_IN
20
Under
V3AUX_IN
UVLO
voltage
lock out
VD
Charge
Pump
V15_IN
UVLO_AUX
7
GND
●PHYSICAL DIMENSIONS
●PIN FUNCTION
PIN No
1
PIN NAME
SYSR
V3_IN
PIN FUNCTION
Logic input pin
V3 input pin
4.0 0.1
2
D4156
3
V3
V3 output pin
4
V3_IN
V3 input pin
5
V3
V3 output pin
6
7
PERST_IN#
GND
PERST# control input pin (SysReset#)
GND pin
Lot No.
8
9
PERST#
CPUSB#
CPPE#
V15
V15_IN
V15
V15_IN
V3AUX
TEST
Logic output pin
Logic input pin
Logic input pin
V15 output pin
V15 input pin
V15 output pin
V15 input pin
V3AUX output pin
Test pin
S
10
11
12
13
14
15
16
17
0.08 S
2.1 0.1
C0.2
1
5
20
6
V3AUX_IN
V3AUX input pin 1
Reference clock enable signal /
Power good signal (No delay)
Must be open or GND.
Enable input pin
18
RCLKEN
16
10
19
20
N.C.
EN
15
11
1.0
+0.05
-0.04
0.25
0.5
VQFN020V4040 Package (Unit:mm)
www.rohm.com
2009.05 - Rev.A
6/23
c
○ 2009 ROHM Co., Ltd. All rights reserved.