Technical Note
BD4155FV
●BLOCK DIAGRAM
V3_IN
V3-1 3.3V/1.30A
4
5
6
7
VD
3.3V
3.3V
V3-2
V3_IN2
TSD,CL,UVLO
VD
V3AUX_IN
3.3V AUX/275mA
V3AUX
18
17
TSD,CL,UVLO_AUX
V15_IN1
V15_IN2
V15-1 1.5V/625mA
15
16
13
14
1.5V
V15-2
PLT_RST#(from host)
1
2
8
EC_RST#(from host)
V3AUX_IN
PERST#(to card)
Power
good
VD
(from card) CPPE#
(from card) CPUSB#
(from host) SYSR
12
11
3
Input
logic
PLL_CLKREQ#(to PLL)
EC_CLKREQ#(from card)
19
EN,SYSR
CPUSB#
CPPE#
TSD,CL,UVLO
20
9
TSD
Thermal
protection
V3AUX_IN
V3AUX_IN
V3_IN,V3AUX_IN,V15_IN
EC_CLKEN#(from host)
V3,V3AUX,V15
Reference
Block
CL
UVLO
Under
V3_IN
V3AUX_IN
V15_IN
voltage
UVLO_AUX
Charge
Pump
lock out
VD
10
GND
●Pin Configration
●Pin Function
PIN No
1
PIN NAME
PIN FUNCTION
PLT_RST#
EC_RST#
SYSR
V3_IN1
V3_IN2
V3_1
Logic input pin (from HOST)
Logic input pin (from HOST)
Logic input pin
V3 input pin 1
V3 input pin 2
V3 output pin 1
V3 output pin 2
Logic output pin
Logic input pin (from HOST)
GND pin
Logic input pin
Logic input pin
V15 output pin 1
V15 output pin 2
V15 input pin 1
V15 input pin 2
V3AUX output pin
V3AUX input pin 1
PLT_RST#
1
2
20
19
18
17
16
15
14
13
12
11
EC_CLKREQ#
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PLL_CLKREQ#
V3AUX_IN1
V3AUX
EC_RST#
SYSR
3
V3_IN1
V3_IN2
4
V3_2
PERST#
EC_CLKEN#
GND
CPUSB#
CPPE#
V15_1
5
V15_IN2
V15_IN1
V15_2
V3_1
V3_2
6
7
V15_2
8
PERST#
EC_CLKEN#
GND
V15_1
V15_IN1
V15_IN2
V3AUX
V3AUX_IN
9
CPPE#
10
CPUSB#
PLL_CLKREQ# Clock enable signal (to PLL)
EC_CLKREQ# Logic input pin (from CARD)
SSOP-B20 Package
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
2010.04 - Rev.B
7/16