Technical Note
BD3540NUV, BD3541NUV
●Operation of Each Block
・AMP
This is an error amp that compares the reference voltage (0.65V) with Vo to drive the output Nch FET (Ron=100mΩ～
400mΩ). Frequency optimization helps to realize rapid transient response, and to support the use of ceramic capacitors
on the output. AMP input voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN is
OFF, or when UVLO is active, output goes LOW and the output of the NchFET switches OFF.
・EN
The EN block controls the regulator’s ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is
maintained at 0μA, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the
NRCS pin Vo, thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no
electrical connection is required (e.g., between the VCC pin and the ESD prevention Diode), module operation is
independent of the input sequence.
・UVLO
To prevent malfunctions that can occur during a momentary decrease in VCC, the UVLO circuit switches the output OFF,
and (like the EN block) discharges NRCS and Vo. Once the UVLO threshold voltage (TYP2.5V) is reached, the power-on
reset is triggered and output continues.
・CURRENT LIMIT
When output is ON, the current limit function monitors the internal IC output current against the parameter value (2.0A or
more:BD3540NUV). When current exceeds this level, the current limit module lowers the output current to protect the
load IC. When the overcurrent state is eliminated, output voltage is restored to the parameter value.
・NRCS (Non Rush Current on Start-up)
The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up
can be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as a
20μA (TYP) constant current source to charge the external capacitor. Output start time is calculated via formula (1) below.
0.65V
t = C
・・・(1)
20μA
Tracking sequence is available by connecting the output voltage of external power supply instead of external capacitor.
And then, ratio-metric sequence is also available by changing the resistor division ratio of external power supply output
voltage. (See the next page)
・TSD (Thermal Shut down)
The shutdown (TSD) circuit automatically switches output OFF when the chip temperature gets too high, thus serving to
protect the IC against “thermal runaway” and heat damage. Because the TSD circuit is provided to shut down the IC in
the presence of extreme heat, in order to avoid potential problems with the TSD, it is crucial that the Tj (max) parameter
not be exceeded in the thermal design.
・VIN
The VIN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical
connection (such as between the VCC pin and the ESD protection Diode) is necessary, VIN operates independent of the
input sequence. However, since an output NchFET body Diode exists between VIN and Vo, a VIN-Vo electric (Diode)
connection is present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to VIN from Vo.
・PGOOD
It outputs the output voltage (Vo). PGOOD pin (open drain) is used to pull up the 100kΩ resistor. PGOOD will be
judged HIGH between the FB voltage 0.585V(TYP) to 0.715V(TYP), and will be judged LOW if the voltage is out of range.
・PGDLY
It is available to set PGOOD output delay. PGDLY pin should be connected to 100pF capacitor.
PGOOD delay time id determined by the following formula.
C(pF)×0.75
tpgdly=
(μsec)
Ipgdly (μA)
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.04 - Rev.B
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