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BCM5228FA4IPF

更新时间： 2024-01-19 14:49:25
品牌 Logo 应用领域
博通 - BOARDCOM 局域网（LAN）标准以太网：16GBASE-T电信电信集成电路
页数 文件大小 规格书
100页 1108K
描述
10/100BASE-TX/FX Octal Transceiver

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中文翻译

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BCM5228FA4IPF 技术参数

生命周期：End Of Life包装说明：,
Reach Compliance Code：unknown风险等级：5.73
电信集成电路类型：ETHERNET TRANSCEIVER

BCM5228FA4IPF 数据手册

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Data Sheet  
BCM5228  
10/100BASE-TX/FX Octal-Φ™ Transceiver  
GENERAL DESCRIPTION  
FEATURES  
The BCM5228 is an octal 10/100BASE-TX/FX  
transceiver targeted at Fast Ethernet switches. The  
device contains eight full-duplex 10BASE-T/100BASE-  
TX/FX Fast Ethernet transceivers, each of which  
perform all of the physical layer interface functions for  
10BASE-T Ethernet on Category 3, 4, or 5 unshielded  
twisted-pair (UTP) cable and 100BASE-TX Fast  
Ethernet on Category 5 UTP cable. The 100BASE-FX is  
supported at each port through the use of external fiber-  
optic transmit and receive devices.  
•
10BASE-T/100BASE-TX/FX IEEE 802.3u compliant  
Single-chip octal physical interface-RMII to magnetics  
Reduced Media Independent Interface (RMII)  
Option-Serial Media Independent Interface (SMII)  
Option-Source Synchronous SMII (S3MII)  
Fully integrated digital adaptive equalizers  
125-MHz clock generator and timing recovery  
On-chip multimode transmit waveshaping  
Edge-rate control eliminates external filters  
Integrated baseline wander correction  
HP Auto-MDIX  
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The BCM5228 is a highly integrated solution combining  
digital adaptive equalizers, ADCs, phase locked loops,  
line drivers, encoders, decoders, and the required  
support circuitry into a single monolithic CMOS chip. The  
BCM5228 complies with the IEEE 802.3 specification,  
including the auto-negotiation subsections.  
Cable length indication  
Cable noise level indication  
IEEE 802.3υ-compliant auto-negotiation  
Shared MII management interface up to 25 Mbps  
Serial LED status pins  
Programmable parallel LED pins  
The effective use of digital technology in the BCM5228  
design results in robust performance over a broad range  
of operating scenarios. Problems inherent to mixed-  
signal implementations (such as analog offset and on-  
chip noise) are eliminated by employing field-proven  
digital adaptive equalization and digital clock recovery  
techniques.  
Interrupt output capability  
Loopback mode for diagnostics  
IEEE 1149.1 (JTAG) and NAND chain ICT support  
Low-power, dual-supply 2.5V/3.3V CMOS technology  
Compatible with 2.5V/3.3V I/O  
208-pin PQFP and 256-pin FPBGA packages  
APPLICATIONS  
•
Fast Ethernet switches  
Multimode  
Xmt DAC  
TD± {1:8}  
TXD{1:8}  
10BASE-T  
8
PCS  
SSYNC  
Auto-  
MDIX  
Baseline  
Wander  
SSSMII_TXC  
Correction  
100BASE-X  
PCS  
SSSMII_RSYNC  
SSSMII_RXC  
RXD{1:8}  
Digital  
Adaptive  
Equalizer  
RD± {1:8}  
ADC  
8
Auto-Negotiation  
/Link Integrity  
CRS/Link  
INTR/SLED_DO  
LED1{1:8}  
LED2{1:8}  
Detection  
LED/INT  
8
8
Drivers  
REF_CLK  
Clock  
Clock  
Recovery  
Generator  
SSSMII_DIS/SLED_CLK  
MODES/CONTROLS  
Bias  
13  
RDAC  
JTAG  
Generator  
MII  
MDC  
MII  
Registers  
Mgmt  
Control  
JTAG  
Test Logic  
MDIO  
5
Figure 1: Functional Block Diagram  
5228-DS09-405-R  
7/12/04  
16215 Alton Parkway • P.O. Box 57013 • Irvine, CA 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710  
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