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BCM5238BA3KFB PDF预览

BCM5238BA3KFB

更新时间： 2024-11-19 01:13:03
品牌 Logo 应用领域
博通 - BOARDCOM 局域网（LAN）标准以太网：16GBASE-T电信电信集成电路
页数 文件大小 规格书
76页 933K
描述
10/100BASE-TX Octal Transceiver

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中文翻译

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BCM5238BA3KFB 技术参数

生命周期：Active包装说明：,
Reach Compliance Code：compliant风险等级：5.75
电信集成电路类型：ETHERNET TRANSCEIVERBase Number Matches：1

BCM5238BA3KFB 数据手册

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ADVANCE DATA SHEET  
BCM5238  
10/100BASE-TX Octal-Φ™ Transceiver  
GENERAL DESCRIPTION  
FEATURES  
•
10BASE-T/100BASE-TX IEEE 802.3u compliant  
The BCM5238 is an octal 10/100BASE-TX transceiver  
for Fast Ethernet switches. The device contains eight full-  
duplex 10BASE-T/100BASE-TX Fast Ethernet  
transceivers, each of which performs all of the physical  
layer interface functions for 10BASE-T Ethernet on  
Category 3, 4 or 5 unshielded twisted-pair (UTP) cable  
and 100BASE-TX Fast Ethernet on Category 5 UTP  
cable. Pseudo-100BASE-FX mode is supported through  
external fiber-optic tranceivers.  
•
Single-chip octal physical interface—SMII to  
magnetics  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Option—Source Synchronous SMII (SSSMII)  
Fully integrated digital adaptive equalizers  
125-MHz clock generator and timing recovery  
On-chip multimode transmit waveshaping  
Edge-rate control eliminates external filters  
HP auto-MDIX  
Cable length Indication  
Cable noise level Indication  
The BCM5238 is a highly integrated solution using 0.18-  
micron technology, combining digital adaptive  
equalizers, ADCs, phase locked loops, line drivers,  
encoders, decoders and all the required support circuitry  
into a single monolithic CMOS chip. The BCM5238  
complies with the IEEE 802.3 specification, including the  
auto-negotiation subsections.  
IEEE 802.3u-compliant auto-negotiation  
Shared MII management interface up to 25 Mbps  
Programmable serial LED pins  
Programmable parallel LED pins  
Interrupt output capability  
Loopback mode for diagnostics  
IEEE 1149.1 (JTAG) and NAND-chain ICT support  
Low-power dual-supply 2.5V/1.8V CMOS technology  
Compatible with 3.3 V I/O  
The BCM5238 design results in robust performance over  
a broad range of operating scenarios. Problems inherent  
to mixed-signal implementations, such as analog offset  
and on-chip noise, are eliminated by employing field-  
proven digital adaptive equalization and digital clock  
recovery techniques.  
128 MQFP and 256-pin FBGA package  
APPLICATIONS  
•
Fast Ethernet switches  
Multimode  
Xmt DAC  
TD± ±{1:8}  
TXD{1:8}  
10BASE-T  
PCS  
8
8
SSYNC  
SSSMII_TXC  
Auto  
MDIX  
Baseline  
Wander  
Correction  
100BASE-X  
PCS  
SSSMII_RSYNC  
SSSMII_RXC  
RXD{1:8}  
Digital  
Adaptive  
Equalizer  
RD± ±{1:8}  
ADC  
Auto-Negotiation  
/Link Integrity  
CRS/Link  
Detection  
INTR/SLED_DO  
LED1{1:8}  
LED/INT  
Drivers  
8
8
LED2{1:8}  
REF_CLK  
Clock  
Recovery  
Clock  
Generator  
SSSMII_DIS/SLED_CLK  
MODES/CONTROLS  
Bias  
Generator  
13  
RDAC  
MII  
Mgmt  
Control  
MDC  
MII  
Registers  
JTAG  
Test Logic  
MDIO  
JTAG  
5
Figure 1: Functional Block Diagram  
5238-DS03-405-R  
16215 Alton Parkway • P.O. Box 57013 • Irvine, California 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710  
1/31/03  
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