Datasheet > BCM43907KWBGT

BCM43907KWBGT

更新时间： 2022-02-26 12:46:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
128页	2500K
描述
WICEDâ¢ IEEE 802.11 a/b/g/n SoC with an Embedded Applications Processor

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BCM43907KWBGT 数据手册

BCM43907 Preliminary Data Sheet

Power-Up Sequence and Timing

Section 18: Power-Up Sequence and

Timing

Sequencing of Reset and Regulator Control Signals

The BCM43907 has two signals that allow the host to control power consumption by enabling or disabling the

internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate

proper sequencing of the signals for various operational states (see Figure 39 and Figure 40 on page 123). The

timing values indicated are minimum required values; longer delays are also acceptable.

Description of Control Signals

•

REG_ON: Used by the PMU to power-up the BCM43907. It controls the internal BCM43907 regulators.

When this pin is high, the regulators are enabled and the device is out of reset. When this pin is low the

regulators are disabled.

•

HIB_REG_ON_IN: Used by the Hibernation (HIB) block to power up the internal BCM43907 regulators. If

the HIB_REG_ON_IN pin is low, the regulators are disabled. For the HIB_REG_ON_IN pin to work as

designed, HIB_REG_ON_OUT must be connected to REG_ON.

Note: The BCM43907 has an internal power-on reset (POR) circuit. The device will be held in reset

for a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold.

Note: The 10%–90% VBAT rise time should not be faster than 40 microseconds. VBAT should be up

before or at the same time as VDDIO. VDDIO should not be present first or be held high before VBAT

is high.

Broadcom^®

March 12, 2016 • 43907-DS104-R

Page 122

BROADCOM CONFIDENTIAL

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