Datasheet > BCM43364KUBG

BCM43364KUBG

更新时间： 2022-02-26 11:56:41

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
68页	5794K
描述
Single-band 2.4 GHz IEEE 802.11b/g/n

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数据手册

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BCM43364KUBG 数据手册

PRELIMINARY

CYW43364

Figure 3. Typical Power Topology (1 of 2)

SR_VDDBAT5V

VBAT

WL RF—TX Mixer and PA

Mini PMU

CYW43364

1.2V

Internal VCOLDO

1.2V

WL RF—LOGEN

WL RF—RX LNA

WL RF—ADC REF

WL RF—TX

80 mA (NMOS)

Internal RXLDO

10 mA (NMOS)

VBAT:

Operational:

Performance:

2.4V—4.8V

3.0V—4.8V

VDD1P35

Internal ADCLDO

10 mA (NMOS)

Absolute Maximum: 5.5V

VDDIO

Operational:

Internal TXLDO

80 mA (PMOS)

1.2V

1.8V—3.3V

1.35V

Internal AFELDO

80 mA (NMOS)

WL RF—AFE and TIA

Core Buck

Regulator

10 mA average,

> 10 mA at start‐up

WL RF—RFPLL PFD and MMD

SR_VLX

Mini PMU is placed

in WL radio

Int_SR_VBAT

Peak: 370 mA

WLRF_XTAL_

VDD1P2

Avg: 170 mA

2.2 uH

(320 mA)

SW1

600 @

100 MHz

0603

WL RF—XTAL

1.2V

LDO_VDD_1P5

LNLDO

SR_VBAT5V

(100 mA)

VBAT

GND

4.7 uF

0402

VOUT_LNLDO

0.1 uF

0201

SR_PVSS

2.2 uF

0402

PMU_VSS

WCC_VDDIO

LPLDO1

(5 mA)

1.1V

(40 mA)

WLAN/CLB/Top, Always On

WL OTP

VDDC1

VDDC2

1.3V, 1.2V,

or 0.95V

(AVS)

CL LDO

Peak: 200 mA

Avg: 80 mA

(Bypass in deep‐

sleep)

2.2 uF

0402

VOUT_CLDO

WL Digital and PHY

WL VDDM (SROMs & AOS)

WL_REG_ON

o_wl_resetb

Power switch

No power switch

Supply ball

Supply bump/pad

Ground bump/pad

External to chip

Ground ball

No dedicated power switch, but internal power‐

down modes and block‐specific power switches

WLAN reset balls

Document Number: 002-14781 Rev. *C

Page 7 of 68

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