B10011S-MFPG3

更新时间： 2024-02-09 03:51:17

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
12页	249K
描述
CAN Transceiver, 1-Trnsvr, PDSO16, LEAD FREE, SO-16

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B10011S-MFPG3 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.75
数据速率：	250 Mbps	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	9.9 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	16	收发器数量：	1
最高工作温度：	105 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	5,7/32 V	认证状态：	Not Qualified
座面最大高度：	1.75 mm	子类别：	Network Interfaces
标称供电电压：	5 V	表面贴装：	YES
电信集成电路类型：	INTERFACE CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	3.8 mm
Base Number Matches：	1

B10011S-MFPG3 数据手册

Figure 6-3. Implementation of a Power Filter and Over Clamps

From battery

(cl. 15)

To V_CC(pin 13)

22 µF

33V

Ground

To pin 10

7. Application Hints

As an interface between CAN controllers and a two-wire data bus system for serial data inter-

change, this device is adapted to a special high-level, low-speed transmission system, which is

useful in harsh environments. High immunity against ground offset and interference voltages on

the bus have been the design goals for this device, rather than low power consumption or a min-

imum of external components. An error detection scheme is implemented in the receiver part to

give quick information to the controller in case of faults occurring on the bus. Thus, the controller

is able to start a search cycle in order to look for the possibility of single-wire operation or to dis-

able the station from the bus.

An automatic error-signal end is not feasible because parts of the system are disabled during

single-wire operation. Therefore, the controller has to carry out short tests by switching to the

two-wire state and checking, whether the error signal is still present or not. Errors due to dirty

contacts, shorts between high and low line, or interruptions may not be recognized at all,

because this device does not contain a complete fault computer.

Two control inputs A_seland B_selenable four operation modes (see Table “Operating Modes” on

page 4’). Depending on the nature of the error, the error signal ER is internally generated partly

in the recessive or partly in the dominant transmission state. In order to avoid watching the error

bits bitwise, an open-collector output driver (with a 1-kΩ series resistor) discharges a storage

capacitor, which is charged by a time constant, long enough to hold the 0 state for, e.g., 200 µs,

thus, giving the controller enough time to recognize this status during idle times. Only the charg-

ing resistor may be changed and not the 2.2-nF capacitor. In order to perform a faster error-end

test, the charging resistor may be shorted by an NPN emitter follower or by a tristate output high

for approximately 1 to 2 µs.

The pinout of the device shows a controller side (pins 1 to 8) and a bus side (pins 9 to 16). The

application circuit utilizes an input filter section which is necessary for every station and a bias

section which is needed in two master stations only. Additional slave stations only contain the

driving resistors at pins 11 and 12 (270Ω and 220Ω), the choke coil, and capacitor between pins

13 and 10.

A power filter and overvoltage clamp is highly recommended in order to avoid transmission

errors due to spikes on the 24-V battery voltage.

The input filter is designed as an 2-RC filter for 125 kbit/s and may be changed to 250 kbit/s. Its

good pulse response and good suppression of high frequencies should not be weakened by

omitting one of the capacitors.

B10011S

4749D–AUTO–10/07

1...5 6 789 10 11 12

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